公开(公告)号：US20140085964A1

公开(公告)日：2014-03-27

申请号：US14028942

申请日：2013-09-17

Applicant: ELPIDA MEMORY, INC. ,  SHARP KABUSHIKI KAISHA

Inventor： Takashi NAKANO ,  Yukiko TAMAI ,  Kenji MAE

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79

Abstract: A control circuit controls memory operations such that, in a first rewriting operation in which a resistance state of a variable resistance element is changed from a first state to a second state, a first voltage pulse is applied to both terminals of a memory cell while limiting the amount of current flowing through the variable resistance element to a value smaller than or equal to a certain small amount of current, in a second rewriting operation in which the resistance state of the variable resistance element is changed from the second state to the first state, a second voltage pulse is applied to both terminals of the memory cell, and, in a reading operation in which the resistance state stored in the variable resistance element is read, a third voltage pulse is applied to both terminals of the memory cell.

Abstract translation: 控制电路控制存储器操作，使得在可变电阻元件的电阻状态从第一状态变为第二状态的第一重写操作中，将第一电压脉冲施加到存储单元的两个端子，同时限制 在可变电阻元件的电阻状态从第二状态变为第一状态的第二重写操作中，流过可变电阻元件的电流量小于或等于一定量的电流值 在存储单元的两端施加第二电压脉冲，在读取存储在可变电阻元件中的电阻状态的读取动作中，向存储单元的两端施加第三电压脉冲。