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    Semiconductor device
    3.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09035368B2

    公开(公告)日：2015-05-19

    申请号：US13767193

    申请日：2013-02-14

    Applicant: Elpida Memory, Inc.

    Inventor： Kazuma Shimamoto

    IPC: H01L23/535 ,  H01L27/108

    CPC classification number: H01L27/10814 ,  H01L23/535 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/16 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Provided is a semiconductor device including first and second semiconductor pillars formed on a surface of a semiconductor substrate and aligning in a first direction; a first interconnect extending in a second direction intersecting with the first direction and provided between the first and second semiconductor pillars; and a first contact pad located over the first interconnect, the first contact pad being in contact with and electrically connected to the first semiconductor pillar at a side surface thereof, while being electrically isolated from the second semiconductor pillar.

    Abstract translation: 提供一种半导体器件，包括形成在半导体衬底的表面上并在第一方向上对准的第一和第二半导体柱; 第一互连件，沿与第一方向交叉的第二方向延伸并设置在第一和第二半导体柱之间; 以及位于所述第一互连件上方的第一接触焊盘，所述第一接触焊盘在与所述第二半导体柱电隔离的同时与所述第一半导体柱的侧表面接触并电连接。

    Semiconductor device
    4.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09018973B2

    公开(公告)日：2015-04-28

    申请号：US13644388

    申请日：2012-10-04

    Applicant: Elpida Memory, Inc.

    Inventor： Nakaba Kaiwa ,  Yutaka Ikeda

    IPC: H03K19/003 ,  H03H7/40 ,  H04L25/02 ,  H03K21/38

    CPC classification number: G01R35/005 ,  G01R19/0084 ,  G01R27/02 ,  H03H7/40 ,  H03K21/38 ,  H04L25/0278

    Abstract: A device, comprising an output terminal; an output circuit coupled to the output terminal and having an adjustable impedance; and an impedance adjustment circuit adjusting stepwise the adjustable impedance so as to head toward a first reference impedance. The impedance adjustment circuit changes the adjustable impedance by a first amount when the adjustable impedance is within a first range, and changes the adjustable impedance by a second amount when the adjustable impedance is out of the first range. The first amount is smaller than the second amount.

    Abstract translation: 一种装置，包括输出端子; 输出电路，其耦合到所述输出端子并具有可调阻抗; 以及阻抗调节电路，其逐步地调节可调阻抗以朝向第一参考阻抗。 当可调阻抗在第一范围内时，阻抗调节电路将可调阻抗改变第一量，并且当可调阻抗超出第一范围时，阻抗调节电路将可调阻抗改变第二量。 第一个数量小于第二个数量。

    Methods for reproducible flash layer deposition
    5.
    发明授权
    Methods for reproducible flash layer deposition 有权

    公开(公告)号：US09012298B2

    公开(公告)日：2015-04-21

    申请号：US13731452

    申请日：2012-12-31

    Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc

    Inventor： Sandra G. Malhotra ,  Hiroyuki Ode ,  Xiangxin Rui

    IPC: H01L21/02 ,  H01G4/008 ,  H01L49/02

    CPC classification number: H01L28/56 ,  H01L28/65 ,  H01L28/75

    Abstract: A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a flash layer between the dielectric layer and the first electrode layer. A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capping layer between the dielectric layer and the second electrode layer. The flash layer and the capping layer can be formed using an atomic layer deposition (ALD) technique. The precursor materials used for forming the flash layer and the capping layer are selected such they include at least one metal-oxygen bond. Additionally, the precursor materials are selected to also include “bulky” ligands.

    Semiconductor device with memory device
    6.
    发明授权
    Semiconductor device with memory device 有权
    具有存储器件的半导体器件

    公开(公告)号：US09001565B2

    公开(公告)日：2015-04-07

    申请号：US13868532

    申请日：2013-04-23

    Applicant: Elpida Memory, Inc.

    Inventor： Noriaki Ikeda

    IPC: G11C11/24 ,  G11C11/401 ,  G11C5/02 ,  G11C11/4097 ,  H01L27/02 ,  H01L27/108 ,  H01L49/02

    CPC classification number: G11C11/401 ,  G11C5/025 ,  G11C11/4097 ,  H01L27/0203 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/91

    Abstract: A memory mat (101) includes a main body portion (200) that includes a first capacitor (203A), a linear conductive film (204) that is formed between the main body portion (200) and a peripheral circuit (104), and a second capacitor (203B) that is formed to be in contact with the conductive film (204) at a bottom of the second capacitor (203B). The first capacitor (203A) is in contact with a contact layer (202) at a bottom of the first capacitor (203A).

    Abstract translation: 存储垫（101）包括主体部分（200），其包括第一电容器（203A），形成在主体部分（200）和外围电路（104）之间的线性导电膜（204），以及 形成为与第二电容器（203B）的底部的导电膜（204）接触的第二电容器（203B）。 第一电容器（203A）与第一电容器（203A）底部的接触层（202）接触。

    Sense amplifier circuit and semiconductor device
    7.
    发明授权
    Sense amplifier circuit and semiconductor device 有权
    感应放大器电路和半导体器件

    公开(公告)号：US08982652B2

    公开(公告)日：2015-03-17

    申请号：US13675431

    申请日：2012-11-13

    Applicant: Elpida Memory, Inc.

    Inventor： Kazuhiko Kajigaya ,  Soichiro Yoshida ,  Yasutoshi Yamada

    IPC: G11C7/02 ,  G11C7/06 ,  G11C11/4091 ,  G11C5/14 ,  G11C7/10 ,  G11C7/00

    CPC classification number: G11C7/06 ,  G11C5/147 ,  G11C7/065 ,  G11C7/067 ,  G11C7/1087 ,  G11C11/4091

    Abstract: A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes.

    Abstract translation: 本发明的单端读出放大器电路包括第一和第二MOS晶体管以及第一和第二预充电电路。 第一MOS晶体管将位线驱动到预定电压并且切换位线和感测节点之间的连接，并且栅极连接到感测节点的第二MOS晶体管经由第一MOS晶体管放大信号。 第一预充电电路将位线预充电到第一电位，而第二预充电电路将感测节点预充电到第二电位。 在感测操作之前，当控制上述栅极电压降低时，位线被驱动到预定电压。 适当地设定预定电压，使得可以在电荷转移/分配模式之间的变化点附近获得在高电平和低电平之间的感测节点处的所需电压差。

    DRAM MIM capacitor using non-noble electrodes
    8.
    发明授权
    DRAM MIM capacitor using non-noble electrodes 有权
    DRAM MIM电容器采用非贵金属电极

    公开(公告)号：US08969169B1

    公开(公告)日：2015-03-03

    申请号：US14033326

    申请日：2013-09-20

    Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc

    Inventor： Hanhong Chen ,  David Chi ,  Imran Hashim ,  Mitsuhiro Horikawa ,  Sandra G. Malhotra

    IPC: H01L21/00 ,  H01L49/02

    CPC classification number: H01L28/56 ,  H01L27/108 ,  H01L27/1085 ,  H01L28/40 ,  H01L28/75 ,  H01L28/82

    Abstract: A method for forming a capacitor stack includes forming a first bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. Optionally, an oxygen-rich metal oxide layer is formed above the dielectric layer. Optionally, a third top electrode layer is formed above the oxygen-rich metal oxide layer. The third top electrode layer includes a conductive metal oxide material. A fourth top electrode layer is formed above the third top electrode layer. The fourth top electrode layer includes a conductive metal nitride material.

    Abstract translation: 形成电容器堆叠的方法包括形成包括导电金属氮化物材料的第一底部电极层。 在第一底部电极层的上方形成第二底部电极层。 第二底部电极层包括导电金属氧化物材料，其中导电金属氧化物材料的晶体结构促进随后沉积的介电层的期望的高k结晶相。 在第二底部电极层的上方形成电介质层。 任选地，在介电层上方形成富氧金属氧化物层。 可选地，在富氧金属氧化物层的上方形成第三上电极层。 第三顶部电极层包括导电金属氧化物材料。 第四上电极层形成在第三顶电极层的上方。 第四顶部电极层包括导电金属氮化物材料。

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