公开(公告)号：US08954721B2

公开(公告)日：2015-02-10

申请号：US13314733

申请日：2011-12-08

申请人： Eberhard Amann ,  Frank Haverkamp ,  Thomas Huth ,  Jan Kunigk

发明人： Eberhard Amann ,  Frank Haverkamp ,  Thomas Huth ,  Jan Kunigk

IPC分类号： G06F9/00 ,  G06F9/24 ,  G06F15/177 ,  G06F15/00 ,  G06F15/167

CPC分类号： G06F9/4405 ,  G06F9/4401 ,  G06F9/4403 ,  G06F9/44505 ,  G06F12/00

摘要： Mechanisms, in a multi-chip data processing system, for performing a boot process for booting each of a plurality of processor chips of the multi-chip data processing system are provided. With these mechanisms, a multi-chip agnostic isolated boot phase operation is performed, in parallel, to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system. A multi-chip aware isolated boot phase operation of each of the processor chips is performed in parallel, where each of the processor chips has its own separately configured address space. In addition, a unified configuration phase operation is performed to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip.

摘要翻译： 提供了在多芯片数据处理系统中用于执行用于引导多芯片数据处理系统的多个处理器芯片中的每一个的引导过程的机制。 利用这些机制，并行地执行多芯片不可知的隔离引导相位操作，以执行多个处理器芯片中的每一个的初始启动，就好像每个处理器芯片是多芯片数据中的唯一处理器芯片 处理系统。 并行执行每个处理器芯片的多芯片感知隔离引导阶段操作，其中每个处理器芯片具有其自己独立配置的地址空间。 此外，执行统一配置阶段操作以从多个处理器芯片中选择主处理器芯片，并且配置多个处理器芯片中的其他处理器芯片作为由主处理器芯片控制的从处理器芯片。

公开(公告)号：US20130060986A1

公开(公告)日：2013-03-07

申请号：US13226360

申请日：2011-09-06

申请人： Eberhard Amann ,  Frank Haverkamp ,  Jan Kunigk ,  Thomas Huth

发明人： Eberhard Amann ,  Frank Haverkamp ,  Jan Kunigk ,  Thomas Huth

IPC分类号： G06F13/36

CPC分类号： G06F13/00 ,  G06F15/177

摘要： Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated.

公开(公告)号：US08954639B2

公开(公告)日：2015-02-10

申请号：US13226360

申请日：2011-09-06

申请人： Eberhard Amann ,  Frank Haverkamp ,  Jan Kunigk ,  Thomas Huth

发明人： Eberhard Amann ,  Frank Haverkamp ,  Jan Kunigk ,  Thomas Huth

IPC分类号： G06F13/00 ,  G06F9/00

CPC分类号： G06F13/00 ,  G06F15/177

摘要： Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated.

摘要翻译： 在多处理器系统中将链路校准和动态拓扑发现集成在多处理器系统中建立多个处理器中的第一个作为集成链路校准和动态拓扑发现的指导者。 多个高速互连将多个处理器彼此连接。 导向器处理器经由共享硬件资源引导多个高速互连中的每一个的校准。 共享硬件资源在多个处理器之间共享。 基于被校准的多个高速互连中的每一个的结果来校准多个高速互连中的每一个来增量地发现多处理器系统的拓扑。

公开(公告)号：US20130151829A1

公开(公告)日：2013-06-13

申请号：US13314733

申请日：2011-12-08

申请人： Eberhard Amann ,  Frank Haverkamp ,  Thomas Huth ,  Jan Kunigk

发明人： Eberhard Amann ,  Frank Haverkamp ,  Thomas Huth ,  Jan Kunigk

IPC分类号： G06F9/00

CPC分类号： G06F9/4405 ,  G06F9/4401 ,  G06F9/4403 ,  G06F9/44505 ,  G06F12/00

摘要： Mechanisms, in a multi-chip data processing system, for performing a boot process for booting each of a plurality of processor chips of the multi-chip data processing system are provided. With these mechanisms, a multi-chip agnostic isolated boot phase operation is performed, in parallel, to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system. A multi-chip aware isolated boot phase operation of each of the processor chips is performed in parallel, where each of the processor chips has its own separately configured address space. In addition, a unified configuration phase operation is performed to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip.

公开(公告)号：US20130060978A1

公开(公告)日：2013-03-07

申请号：US13592406

申请日：2012-08-23

申请人： Eberhard Amann ,  Frank Haverkamp ,  Jan Kunigk ,  Thomas Huth

发明人： Eberhard Amann ,  Frank Haverkamp ,  Jan Kunigk ,  Thomas Huth

IPC分类号： G06F13/00

CPC分类号： G06F13/00 ,  G06F15/177

摘要： Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated.

摘要翻译： 在多处理器系统中将链路校准和动态拓扑发现集成在多处理器系统中建立多个处理器中的第一个作为集成链路校准和动态拓扑发现的指导者。 多个高速互连将多个处理器彼此连接。 导向器处理器经由共享硬件资源引导多个高速互连中的每一个的校准。 共享硬件资源在多个处理器之间共享。 基于被校准的多个高速互连中的每一个的结果来校准多个高速互连中的每一个来增量地发现多处理器系统的拓扑。

公开(公告)号：US08996770B2

公开(公告)日：2015-03-31

申请号：US13592406

申请日：2012-08-23

申请人： Eberhard Amann ,  Frank Haverkamp ,  Jan Kunigk ,  Thomas Huth

发明人： Eberhard Amann ,  Frank Haverkamp ,  Jan Kunigk ,  Thomas Huth

IPC分类号： G06F13/00

CPC分类号： G06F13/00 ,  G06F15/177

摘要： Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated.

公开(公告)号：US08032740B2

公开(公告)日：2011-10-04

申请号：US12166182

申请日：2008-07-01

申请人： Frank Haverkamp ,  Gerald Kreissig ,  Joshua W. Boyer ,  Shaun A. Wetzstein

发明人： Frank Haverkamp ,  Gerald Kreissig ,  Joshua W. Boyer ,  Shaun A. Wetzstein

IPC分类号： G06F9/00 ,  G06F12/00 ,  G06F9/44 ,  G06F9/445

CPC分类号： G06F8/65

摘要： A method, apparatus and program storage device for updating a non-volatile memory in an embedded system is provided. The invention includes detaching the non-volatile memory from all expectable non-volatile memory references, creating a temporary, volatile-memory file system for allocation of volatile memory space as needed for the non-volatile memory update process, copying all procedural code required to perform the non-volatile memory update into the volatile memory, changing the system search path definitions temporarily to point to the volatile memory, and performing the non-volatile memory update.

摘要翻译： 提供了一种用于更新嵌入式系统中的非易失性存储器的方法，装置和程序存储装置。 本发明包括将非易失性存储器从所有可预期的非易失性存储器引用中分离出来，创建用于非易失性存储器更新过程所需的用于分配易失性存储器空间的临时易失性存储器文件系统，复制所需的所有程序代码 执行非易失性存储器更新到易失性存储器中，暂时改变系统搜索路径定义以指向易失性存储器，并执行非易失性存储器更新。

公开(公告)号：US07409539B2

公开(公告)日：2008-08-05

申请号：US11197568

申请日：2005-08-04

申请人： Andreas Arnez ,  Joern Engel ,  Frank Haverkamp

发明人： Andreas Arnez ,  Joern Engel ,  Frank Haverkamp

IPC分类号： G06F9/445 ,  G06F15/177

CPC分类号： G06F11/1417 ,  G06F11/1658 ,  G06F11/1666

摘要： The present invention relates to boot code processing of a computer system, and in particular to a method and respective system for managing boot code of a computer system, wherein the system comprises at least a first and a redundant second boot memory portion, and wherein the system is booted from one of said portions, referred to as the active booting portion, the other boot portion being in a stand-by mode and being referred to as inactive boot portion. In order to increase the robustness of a computer system against failures due to errors in boot code updates it is proposed to perform the steps of: a) booting the system from said first one (default) of said two boot memory portions; b) verifying the correctness of the boot procedure, if not correct; c1) re-booting from said second boot portion, and c2) replicating the boot code from the active boot memory portion to the non-active boot memory portion, if correct; d) replicating the boot code from the active boot memory portion to the non-active boot memory portion; e) run normal operation mode.

摘要翻译： 本发明涉及计算机系统的引导代码处理，特别涉及用于管理计算机系统的引导代码的方法和相应的系统，其中该系统至少包括第一和第二引导存储器部分，并且其中， 系统从被称为主动引导部分的所述部分之一引导，另一个引导部分处于待机模式，并被称为非活动引导部分。 为了增加计算机系统对由于引导代码更新中的错误而引起的故障的鲁棒性，建议执行以下步骤：a）从所述两个引导存储器部分的第一个（默认）引导系统; b）验证引导程序的正确性，如果不正确; c1）从所述第二引导部分重新引导，以及c2）如果正确，将所述引导代码从所述主动引导存储器部分复制到所述非活动引导存储器部分; d）将所述启动代码从所述主动引导存储器部分复制到所述非活动引导存储器部分; e）运行正常运行模式。

公开(公告)号：US20070033387A1

公开(公告)日：2007-02-08

申请号：US11197568

申请日：2005-08-04

申请人： Andreas Arnez ,  Joern Engel ,  Frank Haverkamp

发明人： Andreas Arnez ,  Joern Engel ,  Frank Haverkamp

IPC分类号： G06F9/00

CPC分类号： G06F11/1417 ,  G06F11/1658 ,  G06F11/1666

摘要： The present invention relates to boot code processing of a computer system, and in particular to a method and respective system for managing boot code of a computer system, wherein the system comprises at least a first and a redundant second boot memory portion, and wherein the system is booted from one of said portions, referred to as the active booting portion, the other boot portion being in a stand-by mode and being referred to as inactive boot portion. In order to increase the robustness of a computer system against failures due to errors in boot code updates it is proposed to perform the steps of: a) booting the system from said first one (default) of said two boot memory portions; b) verifying the correctness of the boot procedure, if not correct; c1) re-booting from said second boot portion, and c2) replicating the boot code from the active boot memory portion to the non-active boot memory portion, if correct; d) replicating the boot code from the active boot memory portion to the non-active boot memory portion; e) run normal operation mode.

摘要翻译： 本发明涉及计算机系统的引导代码处理，特别涉及用于管理计算机系统的引导代码的方法和相应的系统，其中该系统至少包括第一和第二引导存储器部分，并且其中， 系统从被称为主动引导部分的所述部分之一引导，另一个引导部分处于待机模式，并被称为非活动引导部分。 为了提高计算机系统由于引导代码更新中的错误导致的故障的鲁棒性，建议执行以下步骤：a）从所述两个引导存储器部分的第一个（默认）引导系统; b）验证引导程序的正确性，如果不正确; c1）从所述第二引导部分重新引导，以及c2）如果正确，将所述引导代码从所述主动引导存储器部分复制到所述非活动引导存储器部分; d）将所述启动代码从所述主动引导存储器部分复制到所述非活动引导存储器部分; e）运行正常运行模式。

公开(公告)号：US08843785B2

公开(公告)日：2014-09-23

申请号：US13494314

申请日：2012-06-12

申请人： Frank Haverkamp ,  Heiko Michel ,  Joerg-Stephan Vogt

发明人： Frank Haverkamp ,  Heiko Michel ,  Joerg-Stephan Vogt

IPC分类号： G06F11/00 ,  G06F11/36 ,  G06F21/74

CPC分类号： G06F21/74 ,  G06F11/3656

摘要： Mechanisms, in a processor chip, are provided for obtaining debug data from on-chip logic of the processor chip while the processor chip is in a secure mode of operation. The processor chip is placed into a secure mode of operation in which access to internal logic of the processor chip to control the internal logic of the processor chip, by mechanisms external to the processor chip, is disabled on a debug interface of the processor chip. A triggering condition of the processor chip is detected that is a trigger for initiated debug data collection from the on-chip logic. Debug data collection is performed from the on-chip logic to generate debug data. Data is output, by the processor chip to an external mechanism, on the debug interface based on the debug data.

摘要翻译： 在处理器芯片中提供用于在处理器芯片处于安全操作模式时从处理器芯片的片上逻辑获得调试数据的机制。 处理器芯片被放置在安全操作模式中，其中通过处理器芯片外部的机制来控制处理器芯片的内部逻辑的内部逻辑的访问在处理器芯片的调试接口上禁用。 检测到处理器芯片的触发条件，该触发条件是从片上逻辑引发的调试数据收集的触发。 从片上逻辑执行调试数据采集，以生成调试数据。 数据由处理器芯片输出到外部机制，在调试接口上基于调试数据。