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1.发明授权Method and apparatus for adjustment of time delays in synchronous clocked bus systems 失效用于调整同步时钟总线系统中的时间延迟的方法和装置公开(公告)号：US06625176B1
公开(公告)日：2003-09-23
申请号：US09301821
申请日：1999-04-29
IPC分类号： B41M524
CPC分类号： H04L25/14 , H04L69/14 , H04Q2213/13036 , H04Q2213/13103 , H04Q2213/13106 , H04Q2213/13208 , H04Q2213/13209 , H04Q2213/13213 , H04Q2213/13216 , H04Q2213/1329 , H04Q2213/1331 , H04Q2213/1332 , H04Q2213/1336 , H04Q2213/13362 , H04Q2213/13389
摘要： A method is provided to adjust time delays and sequence ordering of data channels in synchronous clocked bus systems. In particular, the invention relates to a method to re-synchronize data in respective channels which have a relative delay to each other caused by different path lengths, etc., on the way from sender to receiver. Still more specifically, the invention relates to an apparatus used to eliminate those delays in order to make data usable again on the receiver side. The method can be carried out using standard microprocessors without the need for special hardware implementations. Thus the use of costly and performance intensive ASICs and signal processors can be avoided.
摘要翻译： 提供了一种方法来调整同步时钟总线系统中数据通道的时间延迟和序列排序。 具体地，本发明涉及一种在从发送方到接收方的方式上，在各个信道中重新同步数据的方法，该方法具有由不同的路径长度等引起的彼此之间的相对延迟。 更具体地，本发明涉及一种用于消除那些延迟以便使数据在接收机侧再次可用的装置。 该方法可以使用标准微处理器进行，而不需要特殊的硬件实现。 因此，可以避免使用昂贵且性能强大的ASIC和信号处理器。
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公开(公告)号：US06560201B1
公开(公告)日：2003-05-06
申请号：US09301987
申请日：1999-04-29
IPC分类号： G06F1100
CPC分类号： H04Q11/0457 , H04Q2213/13166 , H04Q2213/13176 , H04Q2213/13204 , H04Q2213/13208 , H04Q2213/13209 , H04Q2213/1327 , H04Q2213/1329 , H04Q2213/1336 , H04Q2213/13389 , Y10S370/904
摘要： Method and apparatus are provided for re-synchronizing a group of B channels in an ISDN network using the BONDING Mode 1 specification. Re-synchronization is achieved without the need to first disconnect the affected group of B channels from the network. Thus, the reliability of the bonded channels is improved while maintaining a simpler architecture than those associated with BONDING Modes 2 and 3. The solution offers improved channel reliability, improved network performance and reduced network load when channel re-synchronization becomes necessary.
摘要翻译： 提供了使用BONDING模式1规范在ISDN网络中重新同步一组B信道的方法和装置。 实现重新同步，而无需首先将受影响的B通道组与网络断开连接。 因此，与保持模式2和3相关联的结构相比，保持结构更简单的结构，提高了绑定信道的可靠性。当需要信道重新同步时，解决方案提供了改进的信道可靠性，改进的网络性能和减少的网络负载。
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公开(公告)号：US08996770B2
公开(公告)日：2015-03-31
申请号：US13592406
申请日：2012-08-23
申请人： Eberhard Amann , Frank Haverkamp , Jan Kunigk , Thomas Huth
发明人： Eberhard Amann , Frank Haverkamp , Jan Kunigk , Thomas Huth
IPC分类号： G06F13/00
CPC分类号： G06F13/00 , G06F15/177
摘要： Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated.
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公开(公告)号：US08954721B2
公开(公告)日：2015-02-10
申请号：US13314733
申请日：2011-12-08
申请人： Eberhard Amann , Frank Haverkamp , Thomas Huth , Jan Kunigk
发明人： Eberhard Amann , Frank Haverkamp , Thomas Huth , Jan Kunigk
IPC分类号： G06F9/00 , G06F9/24 , G06F15/177 , G06F15/00 , G06F15/167
CPC分类号： G06F9/4405 , G06F9/4401 , G06F9/4403 , G06F9/44505 , G06F12/00
摘要： Mechanisms, in a multi-chip data processing system, for performing a boot process for booting each of a plurality of processor chips of the multi-chip data processing system are provided. With these mechanisms, a multi-chip agnostic isolated boot phase operation is performed, in parallel, to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system. A multi-chip aware isolated boot phase operation of each of the processor chips is performed in parallel, where each of the processor chips has its own separately configured address space. In addition, a unified configuration phase operation is performed to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip.
摘要翻译： 提供了在多芯片数据处理系统中用于执行用于引导多芯片数据处理系统的多个处理器芯片中的每一个的引导过程的机制。 利用这些机制，并行地执行多芯片不可知的隔离引导相位操作，以执行多个处理器芯片中的每一个的初始启动，就好像每个处理器芯片是多芯片数据中的唯一处理器芯片 处理系统。 并行执行每个处理器芯片的多芯片感知隔离引导阶段操作，其中每个处理器芯片具有其自己独立配置的地址空间。 此外，执行统一配置阶段操作以从多个处理器芯片中选择主处理器芯片，并且配置多个处理器芯片中的其他处理器芯片作为由主处理器芯片控制的从处理器芯片。
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公开(公告)号：US20130060986A1
公开(公告)日：2013-03-07
申请号：US13226360
申请日：2011-09-06
申请人： Eberhard Amann , Frank Haverkamp , Jan Kunigk , Thomas Huth
发明人： Eberhard Amann , Frank Haverkamp , Jan Kunigk , Thomas Huth
IPC分类号： G06F13/36
CPC分类号： G06F13/00 , G06F15/177
摘要： Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated.
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公开(公告)号：US08954639B2
公开(公告)日：2015-02-10
申请号：US13226360
申请日：2011-09-06
申请人： Eberhard Amann , Frank Haverkamp , Jan Kunigk , Thomas Huth
发明人： Eberhard Amann , Frank Haverkamp , Jan Kunigk , Thomas Huth
CPC分类号： G06F13/00 , G06F15/177
摘要： Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated.
摘要翻译： 在多处理器系统中将链路校准和动态拓扑发现集成在多处理器系统中建立多个处理器中的第一个作为集成链路校准和动态拓扑发现的指导者。 多个高速互连将多个处理器彼此连接。 导向器处理器经由共享硬件资源引导多个高速互连中的每一个的校准。 共享硬件资源在多个处理器之间共享。 基于被校准的多个高速互连中的每一个的结果来校准多个高速互连中的每一个来增量地发现多处理器系统的拓扑。
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公开(公告)号：US20130151829A1
公开(公告)日：2013-06-13
申请号：US13314733
申请日：2011-12-08
申请人： Eberhard Amann , Frank Haverkamp , Thomas Huth , Jan Kunigk
发明人： Eberhard Amann , Frank Haverkamp , Thomas Huth , Jan Kunigk
IPC分类号： G06F9/00
CPC分类号： G06F9/4405 , G06F9/4401 , G06F9/4403 , G06F9/44505 , G06F12/00
摘要： Mechanisms, in a multi-chip data processing system, for performing a boot process for booting each of a plurality of processor chips of the multi-chip data processing system are provided. With these mechanisms, a multi-chip agnostic isolated boot phase operation is performed, in parallel, to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system. A multi-chip aware isolated boot phase operation of each of the processor chips is performed in parallel, where each of the processor chips has its own separately configured address space. In addition, a unified configuration phase operation is performed to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip.
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公开(公告)号：US20130060978A1
公开(公告)日：2013-03-07
申请号：US13592406
申请日：2012-08-23
申请人： Eberhard Amann , Frank Haverkamp , Jan Kunigk , Thomas Huth
发明人： Eberhard Amann , Frank Haverkamp , Jan Kunigk , Thomas Huth
IPC分类号： G06F13/00
CPC分类号： G06F13/00 , G06F15/177
摘要： Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated.
摘要翻译： 在多处理器系统中将链路校准和动态拓扑发现集成在多处理器系统中建立多个处理器中的第一个作为集成链路校准和动态拓扑发现的指导者。 多个高速互连将多个处理器彼此连接。 导向器处理器经由共享硬件资源引导多个高速互连中的每一个的校准。 共享硬件资源在多个处理器之间共享。 基于被校准的多个高速互连中的每一个的结果来校准多个高速互连中的每一个来增量地发现多处理器系统的拓扑。
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