公开(公告)号：US07313508B2

公开(公告)日：2007-12-25

申请号：US10330929

申请日：2002-12-27

申请人： Ebo Croffie ,  Colin Yates ,  Nicholas Eib ,  Christopher Neville ,  Mario Garza ,  Neal Callan

发明人： Ebo Croffie ,  Colin Yates ,  Nicholas Eib ,  Christopher Neville ,  Mario Garza ,  Neal Callan

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： The invention provides a method of performing process window compliant corrections of a design layout. The invention includes an operator performing the following steps: (1) simulating Develop Inspect Critical Dimension (DI CD) at best exposure conditions using the provided original layout pattern; (2) simulating DI CD at predefined boundary exposure conditions using the provided original layout pattern; (3) if the DI CD from step (1) meets the target DI CD definition, and the DI CD from step (2) meets process window specifications, convergence takes place; and (4) modifying the layout pattern and repeating steps (2) through (3) until DI CD from step (2) reaches the specification limit if any portion of step (3) is not achieved.

摘要翻译： 本发明提供了一种执行设计布局的兼容过程窗口校正的方法。 本发明包括一个操作员执行以下步骤：（1）使用提供的原始布局模式在最佳曝光条件下模拟发现检查临界尺寸（DI CD）; （2）使用提供的原始布局图案在预定边界曝光条件下模拟DI CD; （3）如果来自步骤（1）的DI CD符合目标DI CD定义，并且步骤（2）的DI CD符合过程窗口规范，则会发生收敛; （4）如果没有实现步骤（3）的任何部分，则修改布局图案并重复步骤（2）至（3），直到来自步骤（2）的DI CD达到规格极限。

公开(公告)号：US20060281287A1

公开(公告)日：2006-12-14

申请号：US11304871

申请日：2005-12-14

申请人： Colin Yates ,  Christopher Neville

发明人： Colin Yates ,  Christopher Neville

IPC分类号： H01L21/3205

CPC分类号： H01L21/76838 ,  H01L23/53276 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming an aligned connection between a nanotube layer and a raised feature is disclosed. A substrate having a raised feature has spacers formed next to the side of the raised feature. The spacers are etched until the sidewalls of the raised feature are exposed forming a notched feature at the top of the spacers. A patterned nanotube layer is formed such that the nanotube layer overlies the top of the spacer and contacts a side portion of the raised feature in the notched feature. The nanotube layer is then covered with an insulating layer. Then a top portion of the insulating layer is removed to expose a top portion of the etched feature.

公开(公告)号：US06458508B1

公开(公告)日：2002-10-01

申请号：US09792321

申请日：2001-02-23

申请人： Nicholas F. Pasch ,  Shumay X. Dou ,  Colin Yates

发明人： Nicholas F. Pasch ,  Shumay X. Dou ,  Colin Yates

IPC分类号： G03F711

CPC分类号： G03F7/11 ,  H01L21/312

摘要： Increased resolution is available from acid-catalyzed photoresist used in fabricating integrated circuits by inhibiting chemically-basic contaminants from contacting the photoresist placed above an IC structure which emits those chemically-basic contaminants. The inhibition can result from physical barrier characteristics of a barrier layer placed between the contaminant-emitting surface and the overlying layer of photoresist, or the layer of barrier material may contain acid moieties which chemically neutralize the emitted chemically-basic contaminants before the contaminants reach the photoresist.

摘要翻译： 通过抑制化学碱性污染物与放置在发射这些化学碱性污染物的IC结构上方的光致抗蚀剂接触的酸催化光致抗蚀剂，提供了更高的分辨率。 抑制可以由位于污染物发射表面和光致抗蚀剂的上覆层之间的阻挡层的物理屏障特性引起，或者阻挡材料层可含有酸性部分，其在污染物到达之前化学中和所发射的化学碱性污染物 光刻胶。

公开(公告)号：US5863825A

公开(公告)日：1999-01-26

申请号：US940156

申请日：1997-09-29

申请人： Nicholas F. Pasch ,  Marilyn Hwan ,  Richard Osugi ,  Colin Yates ,  Dawn Lee ,  Shumay Dou

发明人： Nicholas F. Pasch ,  Marilyn Hwan ,  Richard Osugi ,  Colin Yates ,  Dawn Lee ,  Shumay Dou

IPC分类号： H01L21/027 ,  H01L23/544 ,  H01L21/76

CPC分类号： H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002

摘要： A method of providing etched alignment marks on a semiconductor workpiece that has a substantially planar surface, such as one that has been polished, for supporting accurate alignment of the workpiece in subsequent process operations. The surface of the semiconductor workpiece includes two layers of materials that abut at the workpiece surface. For example, the workpiece may include a layer of insulative material such as silicon dioxide forming several vias and a layer of conductive material such as tungsten forming plugs in the vias. The method includes etching the substantially planar surface to reduce a height of one of the materials below the height of the other material. For example, the tungstein plugs can be etched to a height that is below the height of the surrounding silicon dioxide. The location where the silicon dioxide abuts the tungsten produces a small bump. This bump then serves as an alignment mark for subsequent operations. Furthermore, such subsequent operations will replicate, and/or enhance, the topographical distinction of the alignment mark.

摘要翻译： 在半导体工件上提供蚀刻的对准标记的方法，其具有基本上平坦的表面，例如已被抛光的表面，用于在随后的工艺操作中支持工件的精确对准。 半导体工件的表面包括在工件表面上邻接的两层材料。 例如，工件可以包括一层绝缘材料，例如形成几个通孔的二氧化硅和一个导电材料层，例如通孔中形成钨的插塞。 该方法包括蚀刻基本上平坦的表面，以将材料之一的高度降低到低于另一材料高度的高度。 例如，钨锡塞可被蚀刻到低于周围二氧化硅高度的高度。 二氧化硅与钨接触的位置产生小的凸起。 然后，该凸块用作后续操作的对准标记。 此外，这样的后续操作将复制和/或增强对准标记的形貌区分。

公开(公告)号：US20060264053A1

公开(公告)日：2006-11-23

申请号：US11304801

申请日：2005-12-14

申请人： Colin Yates

发明人： Colin Yates

IPC分类号： H01L21/311 ,  C23F1/00 ,  B44C1/22

CPC分类号： H01L21/76885 ,  B82Y10/00 ,  H01L21/76838 ,  H01L2221/1094 ,  Y10S977/742

摘要： A method of forming an aligned connection between a nanotube layer and an etched feature is disclosed. An etched feature is formed having a top and a side and optionally a notched feature at the top. A patterned nanotube layer is formed such that the nanotube layer contacts portions of the side and overlaps a portion of the top of the etched feature. The nanotube layer is then covered with an insulating layer. Then a top portion of the insulating layer is removed to expose a top portion of the etched feature.