公开(公告)号：US06425117B1

公开(公告)日：2002-07-23

申请号：US08937296

申请日：1997-09-29

申请人： Nicholas F. Pasch ,  Nicholas K. Eib ,  Colin D. Yates ,  Shumay Dou

发明人： Nicholas F. Pasch ,  Nicholas K. Eib ,  Colin D. Yates ,  Shumay Dou

IPC分类号： G06F1750

CPC分类号： G06F17/5068 ,  G03F1/36

摘要： The system and method performs optical proximity correction on an integrated circuit (IC) mask design by initially performing optical proximity correction on a library of cells that are used to create the IC. The pre-tested cells are imported onto a mask design. All cells are placed a minimum distance apart to ensure that no proximity effects will occur between elements fully integrated in different cells. A one-dimensional optical proximity correction technique is performed on the mask design by performing proximity correction only on those components, e.g., lines, that are not fully integrated within one cell.

摘要翻译： 该系统和方法通过在用于创建IC的单元格库上最初执行光学邻近校正来对集成电路（IC）掩模设计执行光学邻近校正。 预先测试的细胞被导入到面罩设计中。 所有细胞被放置在最小距离之间，以确保在完全集成在不同细胞中的元素之间不会发生邻近效应。 通过仅对在一个单元内未完全集成的那些组件（例如线）执行接近校正来对掩模设计执行一维光学邻近校正技术。

公开(公告)号：US08037429B2

公开(公告)日：2011-10-11

申请号：US11241732

申请日：2005-09-30

申请人： Shumay Dou Shang ,  Lisa Swallow ,  Yuri Granik

发明人： Shumay Dou Shang ,  Lisa Swallow ,  Yuri Granik

IPC分类号： G06F17/50

CPC分类号： G03F1/64 ,  G03F1/36

摘要： A system for producing mask layout data retrieves target layout data defining a pattern of features, or portion thereof and an optimized mask layout pattern that includes a number of printing and non-printing features. Mask layout data for one or more subresolution assist features (SRAFs) is then defined to approximate one or more non-printing features of the optimized mask layout pattern.

摘要翻译： 用于产生掩模布局数据的系统检索定义特征图案或其一部分的图案的目标布局数据以及包括多个打印和非打印特征的优化的掩模布局图案。 然后定义一个或多个子分解辅助特征（SRAF）的掩模布局数据以近似优化的掩模布局图案的一个或多个非打印特征。

公开(公告)号：US06713386B1

公开(公告)日：2004-03-30

申请号：US10025304

申请日：2001-12-19

申请人： Rongxiang Hu ,  Yongbae Kim ,  Sang-Yun Lee ,  Hiroaki Takikawa ,  Shumay Dou ,  Sarah Neuman ,  Philippe Schoenborn ,  Keith Chao ,  Dilip Vijay ,  Kai Zhang ,  Masaichi Eda

发明人： Rongxiang Hu ,  Yongbae Kim ,  Sang-Yun Lee ,  Hiroaki Takikawa ,  Shumay Dou ,  Sarah Neuman ,  Philippe Schoenborn ,  Keith Chao ,  Dilip Vijay ,  Kai Zhang ,  Masaichi Eda

IPC分类号： H01L214763

CPC分类号： H01L21/76831 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76826 ,  H01L21/76829

摘要： A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.

公开(公告)号：US5863825A

公开(公告)日：1999-01-26

申请号：US940156

申请日：1997-09-29

申请人： Nicholas F. Pasch ,  Marilyn Hwan ,  Richard Osugi ,  Colin Yates ,  Dawn Lee ,  Shumay Dou

发明人： Nicholas F. Pasch ,  Marilyn Hwan ,  Richard Osugi ,  Colin Yates ,  Dawn Lee ,  Shumay Dou

IPC分类号： H01L21/027 ,  H01L23/544 ,  H01L21/76

CPC分类号： H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002

摘要： A method of providing etched alignment marks on a semiconductor workpiece that has a substantially planar surface, such as one that has been polished, for supporting accurate alignment of the workpiece in subsequent process operations. The surface of the semiconductor workpiece includes two layers of materials that abut at the workpiece surface. For example, the workpiece may include a layer of insulative material such as silicon dioxide forming several vias and a layer of conductive material such as tungsten forming plugs in the vias. The method includes etching the substantially planar surface to reduce a height of one of the materials below the height of the other material. For example, the tungstein plugs can be etched to a height that is below the height of the surrounding silicon dioxide. The location where the silicon dioxide abuts the tungsten produces a small bump. This bump then serves as an alignment mark for subsequent operations. Furthermore, such subsequent operations will replicate, and/or enhance, the topographical distinction of the alignment mark.

摘要翻译： 在半导体工件上提供蚀刻的对准标记的方法，其具有基本上平坦的表面，例如已被抛光的表面，用于在随后的工艺操作中支持工件的精确对准。 半导体工件的表面包括在工件表面上邻接的两层材料。 例如，工件可以包括一层绝缘材料，例如形成几个通孔的二氧化硅和一个导电材料层，例如通孔中形成钨的插塞。 该方法包括蚀刻基本上平坦的表面，以将材料之一的高度降低到低于另一材料高度的高度。 例如，钨锡塞可被蚀刻到低于周围二氧化硅高度的高度。 二氧化硅与钨接触的位置产生小的凸起。 然后，该凸块用作后续操作的对准标记。 此外，这样的后续操作将复制和/或增强对准标记的形貌区分。

公开(公告)号：US06969683B2

公开(公告)日：2005-11-29

申请号：US10750348

申请日：2003-12-31

申请人： Rongxiang Hu ,  Yongbae Kim ,  Sang-Yun Lee ,  Hiroaki Takikawa ,  Shumay Dou ,  Sarah Neuman ,  Philippe Schoenborn ,  Keith Chao ,  Dilip Vijay ,  Kai Zhang ,  Masaichi Eda

发明人： Rongxiang Hu ,  Yongbae Kim ,  Sang-Yun Lee ,  Hiroaki Takikawa ,  Shumay Dou ,  Sarah Neuman ,  Philippe Schoenborn ,  Keith Chao ,  Dilip Vijay ,  Kai Zhang ,  Masaichi Eda

IPC分类号： H01L21/311 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76831 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76826 ,  H01L21/76829

摘要： A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.

摘要翻译： 提供了一种在电介质层中形成双镶嵌互连的方法。 通常，在电介质中蚀刻第一孔。 在电介质的一部分上形成中毒阻挡层，防止抗蚀剂中毒。 在毒物屏障层上形成图案化掩模。 第二孔被蚀刻到电介质层中，其中第一孔的至少一部分具有与第二孔的至少一部分相同的面积。