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1.发明授权System and method for direct memory access from host without processor intervention wherein automatic access to memory during host start up does not occur 失效在没有处理器干预的情况下直接从主机访问主机的系统和方法，其中不会发生在主机启动期间自动访问存储器公开(公告)号：US07149823B2
公开(公告)日：2006-12-12
申请号：US10651887
申请日：2003-08-29
CPC分类号： G06F13/385 , G06F13/28
摘要： A method and system for allowing a host device (e.g., server) to perform programmed direct accesses to peripheral memory (e.g., flash) located on a peripheral device (e.g., HBA), without the assistance of a microprocessor located on the peripheral device. In a preferred embodiment, new host registers are implemented within controller circuitry of the peripheral device, the host registers being configured to be recognized by host software executed by host. The host device reads and writes to the host registers, which causes appropriate controller hardware to access the peripheral nonvolatile memory accordingly. By creating and implementing the new host registers, an enhanced controller is created that allows a host device to directly access peripheral memory, without peripheral processor assistance.
摘要翻译： 一种用于允许主机设备（例如，服务器）在位于外围设备上的微处理器的帮助下对位于外围设备（例如，HBA）上的外围存储器（例如，闪存）进行编程的直接访问的方法和系统。 在优选实施例中，新的主机寄存器被实现在外围设备的控制器电路内，主机寄存器被配置为由主机执行的主机软件识别。 主机设备读取和写入主机寄存器，这导致适当的控制器硬件相应地访问外设非易失性存储器。 通过创建和实现新的主机寄存器，创建一个增强的控制器，允许主机设备直接访问外围存储器，而无需外设处理器的帮助。
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公开(公告)号：US08631169B2
公开(公告)日：2014-01-14
申请号：US12134985
申请日：2008-06-06
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G06F13/382
摘要： Restoring retired transaction identifiers (TID) associated with Direct Memory Access (DMA) commands without waiting for all DMA traffic to terminate is disclosed. A scoreboard is used to track retired TIDs and selectively restore retired TIDs on the fly. DMA engines fetch a TID, and use it to tag every DMA request. If the request is completed, the TID can be recycled to be used to tag a subsequent request. However, if a request is not completed, the TID is retired. Retired TIDs can be restored without having to wait for DMA traffic to end. Any retired TID value may be mapped to a bit location inside a scoreboard. All processors in the system may have access to read and clear the scoreboard. Clearing the TID scoreboard may trigger a DMA engine to restore the TID mapped to that location, and the TID may be used again.
摘要翻译： 公开了恢复与直接存储器访问（DMA）命令相关联的退出事务标识符（TID），而不等待所有DMA流量终止。 记分牌用于跟踪退休的TID，并有选择地恢复退休的TID。 DMA引擎获取TID，并使用它来标记每个DMA请求。 如果请求完成，则可以回收TID以用于标记后续请求。 但是，如果请求未完成，则TID已退休。 可以恢复退出的TID，而不必等待DMA流量结束。 任何退休的TID值都可以映射到记分板内的位置。 系统中的所有处理器都可以访问读取和清除记分板。 清除TID记分板可能会触发DMA引擎恢复映射到该位置的TID，并且可以再次使用TID。
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公开(公告)号：US20100064072A1
公开(公告)日：2010-03-11
申请号：US12207380
申请日：2008-09-09
申请人： John Sui-kei Tang , Sam Shan-Jan Su , Michael Yu Liu , Daming Jin
发明人： John Sui-kei Tang , Sam Shan-Jan Su , Michael Yu Liu , Daming Jin
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A network arbitration scheme is disclosed that manages device access fairness by selectively and dynamically increasing a requestor queue's likelihood of being serviced. A requestor queue increases its service priority by duplicating a request entry onto a set of priority rings maintained by arbitration hardware in a host bus adapter. Duplication occurs when (1) a requestor's queue fill count (the number of descriptors stored in the queue) exceeds a watermark level or (2) a requestor's queue timer times out. In the case of time-out, the requester in the lower priority ring will duplicate itself in the higher priority ring. Because the arbitration hardware services requesters using a round robin selection scheme, the likelihood of a requestor queue being serviced increases as the number of its duplicate request entries on a priority ring increases. Upon being serviced, the requester is able to perform the requested action.
摘要翻译： 公开了一种网络仲裁方案，其通过选择性地和动态地增加请求者队列被服务的可能性来管理设备访问公平性。 请求者队列通过将请求条目复制到由主机总线适配器中的仲裁硬件维护的一组优先级环上而增加其服务优先级。 当（1）请求者的队列填充计数（存储在队列中的描述符的数量）超过水印级别或（2）请求者的队列定时器超时时，发生重复。 在超时的情况下，优先级较低的环中的请求者将在较高优先级环中重复自身。 由于仲裁硬件服务请求者使用循环选择方案，请求者队列被服务的可能性随着优先级环上的重复请求条目的数量增加而增加。 服务后，请求者能够执行所请求的操作。
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公开(公告)号：US07765336B2
公开(公告)日：2010-07-27
申请号：US11811716
申请日：2007-06-11
IPC分类号： G06F3/00
CPC分类号： H04L49/9042 , H04L49/90
摘要： A hardware-based offload engine is disclosed for mapping protected data into frames. For a write operation, the HBA determines host addresses and the size of data to be read from those addresses. The HBA also determines the frame size and protection scheme for data to be written. A frame transmit engine reads each host descriptor in the host data descriptor list to determine the location and byte count of the data to be read. A DMA engine reads the protection information/scratch area to determine the exact data size used to fill each frame and the protection scheme, and retrieves one or more free frame buffers. Check bytes are inserted alongside the data and stored in free frame buffers. After each frame is filled, the frame transmit engine also generates and stores header information for that frame, and then combines header, data and check bytes for transmission over the network.
摘要翻译： 公开了一种基于硬件的卸载引擎，用于将受保护的数据映射到帧中。 对于写操作，HBA确定要从这些地址读取的数据的主机地址和大小。 HBA还确定要写入的数据的帧大小和保护方案。 帧发送引擎读取主机数据描述符列表中的每个主机描述符，以确定要读取的数据的位置和字节数。 DMA引擎读取保护信息/划痕区域以确定用于填充每个帧和保护方案的确切数据大小，并检索一个或多个空闲帧缓冲区。 检查字节与数据一起插入并存储在空闲帧缓冲区中。 在每个帧被填满之后，帧发送引擎也生成并存储该帧的报头信息，然后组合报头，数据和检查字节以便在网络上传输。
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公开(公告)号：US20080307122A1
公开(公告)日：2008-12-11
申请号：US11811716
申请日：2007-06-11
IPC分类号： G06F13/28
CPC分类号： H04L49/9042 , H04L49/90
摘要： A hardware-based offload engine is disclosed for mapping protected data into frames. For a write operation, the HBA determines host addresses and the size of data to be read from those addresses. The HBA also determines the frame size and protection scheme for data to be written. A frame transmit engine reads each host descriptor in the host data descriptor list to determine the location and byte count of the data to be read. A DMA engine reads the protection information/scratch area to determine the exact data size used to fill each frame and the protection scheme, and retrieves one or more free frame buffers. Check bytes are inserted alongside the data and stored in free frame buffers. After each frame is filled, the frame transmit engine also generates and stores header information for that frame, and then combines header, data and check bytes for transmission over the network.
摘要翻译： 公开了一种基于硬件的卸载引擎，用于将受保护的数据映射到帧中。 对于写操作，HBA确定要从这些地址读取的数据的主机地址和大小。 HBA还确定要写入的数据的帧大小和保护方案。 帧发送引擎读取主机数据描述符列表中的每个主机描述符，以确定要读取的数据的位置和字节数。 DMA引擎读取保护信息/划痕区域以确定用于填充每个帧和保护方案的确切数据大小，并检索一个或多个空闲帧缓冲区。 检查字节与数据一起插入并存储在空闲帧缓冲区中。 在每个帧被填满之后，帧发送引擎也生成并存储该帧的报头信息，然后组合报头，数据和检查字节以便在网络上传输。
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公开(公告)号：US20050050245A1
公开(公告)日：2005-03-03
申请号：US10651887
申请日：2003-08-29
申请人： Eddie Miller , David Duckman , Jim Butler , Daming Jin , John Tang
发明人： Eddie Miller , David Duckman , Jim Butler , Daming Jin , John Tang
IPC分类号： G06F20060101 , G06F13/28 , G06F13/38
CPC分类号： G06F13/385 , G06F13/28
摘要： A method and system for allowing a host device (e.g., server) to perform programmed direct accesses to peripheral memory (e.g., flash) located on a peripheral device (e.g., HBA), without the assistance of a microprocessor located on the peripheral device. In a preferred embodiment, new host registers are implemented within controller circuitry of the peripheral device, the host registers being configured to be recognized by host software executed by host. The host device reads and writes to the host registers, which causes appropriate controller hardware to access the peripheral nonvolatile memory accordingly. By creating and implementing the new host registers, an enhanced controller is created that allows a host device to directly access peripheral memory, without peripheral processor assistance.
摘要翻译： 一种用于允许主机设备（例如，服务器）在位于外围设备上的微处理器的帮助下对位于外围设备（例如，HBA）上的外围存储器（例如，闪存）进行编程的直接访问的方法和系统。 在优选实施例中，新的主机寄存器被实现在外围设备的控制器电路内，主机寄存器被配置为由主机执行的主机软件识别。 主机设备读取和写入主机寄存器，这导致适当的控制器硬件相应地访问外设非易失性存储器。 通过创建和实现新的主机寄存器，创建一个增强的控制器，允许主机设备直接访问外围存储器，而无需外设处理器的帮助。
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7.发明授权Efficient processing of groups of host access requests that may include zero length requests 有权高效处理可能包括零长度请求的主机访问请求组公开(公告)号：US07853735B2
公开(公告)日：2010-12-14
申请号：US11956262
申请日：2007-12-13
IPC分类号： G06F5/00
CPC分类号： G06F13/128
摘要： This is directed to methods and systems for handling access requests from a device to a host. The device may be a device that is part of the host, such as an HBA, an NIC, etc. The device may include a processor which runs firmware and which may generate various host access requests. The host access requests may be, for example, memory access requests, or DMA requests. The device may include a module for executing the host access requests, such as a data transfer block (DXB). The DXB may process incoming host access requests and return notifications of completion to the processor. For various reasons, the processor may from time to time issue null or zero length requests. Embodiments of the present invention ensure that the notifications of completion for all requests, including the zero length requests, are sent to the processor in the same order as the requests.
摘要翻译： 这涉及用于处理从设备到主机的访问请求的方法和系统。 设备可以是作为主机的一部分的设备，诸如HBA，NIC等。设备可以包括运行固件并且可以生成各种主机访问请求的处理器。 主机访问请求可以是例如存储器访问请求或DMA请求。 该设备可以包括用于执行主机访问请求的模块，例如数据传输块（DXB）。 DXB可以处理传入的主机访问请求并将完成的通知返回给处理器。 由于各种原因，处理器可能不时地发出空或零长度的请求。 本发明的实施例确保包括零长度请求的所有请求的完成通知以与请求相同的顺序被发送到处理器。
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8.发明授权公开(公告)号：US06658505B2
公开(公告)日：2003-12-02
申请号：US09874711
申请日：2001-06-05
申请人： Daming Jin , Timothy C. Fischer
发明人： Daming Jin , Timothy C. Fischer
IPC分类号： G06F1300
摘要： A computer hardware system is disclosed for determining during a single clock cycle whether a data buffer having a plurality of entries can accept additional data. The system has multiple stages, having one or more adders/encoders that process the data buffer entries' valid bits in parallel. Groups of entries are associated with first-stage adders/encoders. Valid bits and their complements for entries in each group are received into multiple first-stage adders that compute and output encoded values indicating the number of available entries within each group, or first-stage totals. The adders also encode the first-stage totals such that a saturated count corresponds to a pre-charged state of the first-stage adder. The first-stage totals are then sent to additional stages having adders/encoders that are substantially the same as the first-stage adders/encoders. The additional-stage adders combine the encoded totals from prior stages and determine whether the buffer has available entries.
摘要翻译： 公开了一种用于在单个时钟周期内确定具有多个条目的数据缓冲器是否可以接受附加数据的计算机硬件系统。 该系统具有多个级，具有一个或多个并行处理数据缓冲器条目有效位的加法器/编码器。 条目组与第一级加法器/编码器相关联。 每个组中的条目的有效位及其补码被接收到多个第一阶段加法器中，该第一阶段加法器计算和输出指示每个组中的可用条目数量或第一阶段总数的编码值。 加法器还对第一级总计进行编码，使得饱和计数对应于第一级加法器的预充电状态。 然后将第一级总计发送到具有与第一级加法器/编码器基本相同的加法器/编码器的附加级。 附加级加法器组合来自前一级的编码总计，并确定缓冲区是否具有可用条目。
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公开(公告)号：US06687262B1
公开(公告)日：2004-02-03
申请号：US09510280
申请日：2000-02-21
申请人： Daming Jin , Dean A. Mulla , Douglas J Cutter , Thomas Grutkowski
发明人： Daming Jin , Dean A. Mulla , Douglas J Cutter , Thomas Grutkowski
IPC分类号： H04J300
CPC分类号： G06F9/30043 , G06F9/30025 , G06F9/30032
摘要： The inventive control logic provides the selection signals for a bi-endian rotator MUX. The logic determines the starting point for the data transfer by determining which input register byte is going to Byte 0 of the output register. The control logic passes the starting point to single decoder. The decoded value is then sent to a plurality of MUXs, one for each of the output register bytes. Each of the MUXs is prewired to receive a portion of bits of the decoded value, and the portion is arranged in a particular order. The MUXs then send their respective outputs to the rotator MUX as selection control signals.
摘要翻译： 本发明的控制逻辑为双端旋转器MUX提供选择信号。 该逻辑通过确定哪个输入寄存器字节将转到输出寄存器的字节0来确定数据传输的起始点。 控制逻辑将起始点传递到单个解码器。 然后将解码的值发送到多个MUX，每个MUX为每个输出寄存器字节。 每个MUX被预接线以接收解码值的一部分位，并且该部分以特定顺序排列。 然后，多路复用器将其各自的输出发送到旋转器MUX作为选择控制信号。
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公开(公告)号：US06470374B1
公开(公告)日：2002-10-22
申请号：US09510129
申请日：2000-02-21
申请人： Daming Jin , Dean A. Mulla , Tom Grutkowski
发明人： Daming Jin , Dean A. Mulla , Tom Grutkowski
IPC分类号： G06F750
CPC分类号： G06F7/508 , G06F9/3001 , G06F12/0895 , G06F2207/3832
摘要： The inventive adder can perform carry look-ahead calculations for a bi-endian adder in a cache memory system. The adder can add one of +/−1, 4, 8, or 16 to a loaded value from memory, and the operation can be a 4 or 8 byte add. The inventive adder comprises a plurality of byte adder cells and carry look-ahead (CLA) logic. The adder cells determine which of themselves is the least significant bit (LSB) byte adder cell. The LSB cell then adds one of the increment values to its loaded value. The other cells add 0x00 or 0xFF, depending upon the sign of the increment value, to a loaded value from memory. Each adder performs two adds, one for a carry-in of 0, and the other for a carry in of 1. Both results are sent to a MUX. The CLA logic determines each of the carries, and provides a selection control signal to each MUX. of the different cells.
摘要翻译： 本发明的加法器可以对高速缓冲存储器系统中的双端加法器进行执行预读计算。 加法器可以将+/- 1，4，8或16中的一个添加到存储器的加载值，并且操作可以是4或8字节加法。 本发明的加法器包括多个字节加法器单元和携带预读（CLA）逻辑。 加法器单元确定它们中的哪一个是最低有效位（LSB）字节加法器单元。 LSB单元然后将其中一个增量值添加到其加载值。 其他单元格根据增量值的符号将0x00或0xFF添加到内存中的加载值。 每个加法器执行两个加法，一个用于进位为0，另一个用于进位在1中。两个结果都发送到MUX。 CLA逻辑确定每个载波，并且向每个MUX提供选择控制信号。 的不同细胞。
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