公开(公告)号：US08145805B2

公开(公告)日：2012-03-27

申请号：US12135890

申请日：2008-06-09

申请人： Eddie Miller ,  David James Duckman ,  Nazmul H. Khan

发明人： Eddie Miller ,  David James Duckman ,  Nazmul H. Khan

IPC分类号： G06F13/00

CPC分类号： G06F9/3824 ,  G06F9/3855

摘要： Re-sequencing commands and data between a master and slave device utilizing parallel processing is disclosed. When utilizing parallel processing while reading and writing data, there is a chance that the data will be read or written in an improper order, given the time delays associated with different slave devices and the processing time associated with various commands. Therefore, to retain the speed and improved performance of parallel processing while maintaining data coherency, the instructions and data are re-sequenced and processed in the proper order, and the returned data are re-sequenced and returned to the processor in the proper order.

摘要翻译： 公开了使用并行处理在主设备和从设备之间重新排序命令和数据。 当在读取和写入数据时使用并行处理时，给定与不同从设备相关联的时间延迟和与各种命令相关联的处理时间的情况下，有可能以不正确的顺序读取或写入数据。 因此，为了保持并行处理的速度和提高的性能，同时保持数据一致性，指令和数据以适当的顺序重新排序和处理，并且返回的数据被重新排序并以适当的顺序返回给处理器。

公开(公告)号：US20090006761A1

公开(公告)日：2009-01-01

申请号：US11824349

申请日：2007-06-29

申请人： Steven Gerard LeMire ,  Eddie Miller ,  Eric David Peel

发明人： Steven Gerard LeMire ,  Eddie Miller ,  Eric David Peel

IPC分类号： G06F12/08

CPC分类号： G06F12/0888 ,  G06F12/0862 ,  G06F12/123 ,  G06F12/126

摘要： Embodiments of the present invention are directed to a scheme in which information as to the future behavior of particular software is used in order to optimize cache management and reduce cache pollution. Accordingly, a certain type of data can be defined as “short life data” by using knowledge of the expected behavior of particular software. Short life data can be a type of data which, according to the ordinary expected operation of the software, is not expected to be used by the software often in the future. Data blocks which are to be stored in the cache can be examined to determine if they are short life data blocks. If the data blocks are in fact short life data blocks they can be stored only in a particular short life area of the cache.

摘要翻译： 本发明的实施例涉及一种方案，其中使用关于特定软件的未来行为的信息以便优化高速缓存管理并减少高速缓存污染。 因此，通过使用特定软件的预期行为的知识，可将某种类型的数据定义为“短寿命数据”。 短寿命数据可以是一种类型的数据，根据软件的普通预期操作，预计软件通常不会被使用。 可以检查要存储在高速缓存中的数据块，以确定它们是否是短寿命数据块。 如果数据块实际上是短寿命数据块，则它们可以仅存储在高速缓存的特定短寿命区域中。

公开(公告)号：US07805572B2

公开(公告)日：2010-09-28

申请号：US11824349

申请日：2007-06-29

申请人： Steven Gerard LeMire ,  Eddie Miller ,  Eric David Peel

发明人： Steven Gerard LeMire ,  Eddie Miller ,  Eric David Peel

IPC分类号： G06F12/00

CPC分类号： G06F12/0888 ,  G06F12/0862 ,  G06F12/123 ,  G06F12/126

摘要： Embodiments of the present invention are directed to a scheme in which information as to the future behavior of particular software is used in order to optimize cache management and reduce cache pollution. Accordingly, a certain type of data can be defined as “short life data” by using knowledge of the expected behavior of particular software. Short life data can be a type of data which, according to the ordinary expected operation of the software, is not expected to be used by the software often in the future. Data blocks which are to be stored in the cache can be examined to determine if they are short life data blocks. If the data blocks are in fact short life data blocks they can be stored only in a particular short life area of the cache.

摘要翻译： 本发明的实施例涉及一种方案，其中使用关于特定软件的未来行为的信息以便优化高速缓存管理并减少高速缓存污染。 因此，通过使用特定软件的预期行为的知识，可将某种类型的数据定义为“短寿命数据”。 短寿命数据可以是一种类型的数据，根据软件的普通预期操作，预计软件通常不会被使用。 可以检查要存储在高速缓存中的数据块，以确定它们是否是短寿命数据块。 如果数据块实际上是短寿命数据块，则它们可以仅存储在高速缓存的特定短寿命区域中。

公开(公告)号：US20090307473A1

公开(公告)日：2009-12-10

申请号：US12135890

申请日：2008-06-09

申请人： Eddie MILLER ,  David James Duckman ,  Nazmul H. Khan

发明人： Eddie MILLER ,  David James Duckman ,  Nazmul H. Khan

IPC分类号： G06F9/38

CPC分类号： G06F9/3824 ,  G06F9/3855

摘要： Re-sequencing commands and data between a master and slave device utilizing parallel processing is disclosed. When utilizing parallel processing while reading and writing data, there is a chance that the data will be read or written in an improper order, given the time delays associated with different slave devices and the processing time associated with various commands. Therefore, to retain the speed and improved performance of parallel processing while maintaining data coherency, the instructions and data are re-sequenced and processed in the proper order, and the returned data are re-sequenced and returned to the processor in the proper order.

摘要翻译： 公开了使用并行处理在主设备和从设备之间重新排序命令和数据。 当在读取和写入数据时使用并行处理时，给定与不同从设备相关联的时间延迟和与各种命令相关联的处理时间的情况下，有可能以不正确的顺序读取或写入数据。 因此，为了保持并行处理的速度和提高的性能，同时保持数据一致性，指令和数据以适当的顺序重新排序和处理，并且返回的数据被重新排序并以适当的顺序返回给处理器。

公开(公告)号：US07062615B2

公开(公告)日：2006-06-13

申请号：US10651890

申请日：2003-08-29

申请人： Eddie Miller ,  David James Duckman ,  Jim Donald Butler ,  Khanh Hue Huynh

发明人： Eddie Miller ,  David James Duckman ,  Jim Donald Butler ,  Khanh Hue Huynh

IPC分类号： G06F12/00

CPC分类号： G06F9/526

摘要： A method and system for allowing flexible control of access to a shared memory by multiple requesters. In a preferred embodiment, the invention arbitrates access to flash memory on a HBA between multiple host channels and HBA microprocessors, and eliminates contention possibilities for the flash during write cycles by the allowing a grant to be locked for a period defined by the flash write protocol and timing.

摘要翻译： 一种用于允许灵活控制多个请求者对共享存储器的访问的方法和系统。 在优选实施例中，本发明仲裁在多个主机信道和HBA微处理器之间的HBA上对闪存的访问，并且通过允许将许可锁定在由闪存写协议定义的时间段内，在写周期期间消除闪存的争用可能性 和时机。

公开(公告)号：US20050050283A1

公开(公告)日：2005-03-03

申请号：US10651890

申请日：2003-08-29

申请人： Eddie Miller ,  David Duckman ,  Jim Butler ,  Khanh Huynh

发明人： Eddie Miller ,  David Duckman ,  Jim Butler ,  Khanh Huynh

IPC分类号： G06F20060101 ,  G06F12/00

CPC分类号： G06F9/526

摘要： A method and system for allowing flexible control of access to a shared memory by multiple requesters. In a preferred embodiment, the invention arbitrates access to flash memory on a HBA between multiple host channels and HBA microprocessors, and eliminates contention possibilities for the flash during write cycles by the allowing a grant to be locked for a period defined by the flash write protocol and timing.

摘要翻译： 一种用于允许灵活控制多个请求者对共享存储器的访问的方法和系统。 在优选实施例中，本发明仲裁在多个主机信道和HBA微处理器之间的HBA上对闪存的访问，并且通过允许将许可锁定在由闪存写协议定义的时间段内，在写周期期间消除闪存的争用可能性 和时机。

公开(公告)号：US07149823B2

公开(公告)日：2006-12-12

申请号：US10651887

申请日：2003-08-29

申请人： Eddie Miller ,  David James Duckman ,  Jim Donald Butler ,  Daming Jin ,  John Sui-Kei Tang

发明人： Eddie Miller ,  David James Duckman ,  Jim Donald Butler ,  Daming Jin ,  John Sui-Kei Tang

IPC分类号： G06F13/28 ,  G06F12/00

CPC分类号： G06F13/385 ,  G06F13/28

摘要： A method and system for allowing a host device (e.g., server) to perform programmed direct accesses to peripheral memory (e.g., flash) located on a peripheral device (e.g., HBA), without the assistance of a microprocessor located on the peripheral device. In a preferred embodiment, new host registers are implemented within controller circuitry of the peripheral device, the host registers being configured to be recognized by host software executed by host. The host device reads and writes to the host registers, which causes appropriate controller hardware to access the peripheral nonvolatile memory accordingly. By creating and implementing the new host registers, an enhanced controller is created that allows a host device to directly access peripheral memory, without peripheral processor assistance.

摘要翻译： 一种用于允许主机设备（例如，服务器）在位于外围设备上的微处理器的帮助下对位于外围设备（例如，HBA）上的外围存储器（例如，闪存）进行编程的直接访问的方法和系统。 在优选实施例中，新的主机寄存器被实现在外围设备的控制器电路内，主机寄存器被配置为由主机执行的主机软件识别。 主机设备读取和写入主机寄存器，这导致适当的控制器硬件相应地访问外设非易失性存储器。 通过创建和实现新的主机寄存器，创建一个增强的控制器，允许主机设备直接访问外围存储器，而无需外设处理器的帮助。

公开(公告)号：US20050050245A1

公开(公告)日：2005-03-03

申请号：US10651887

申请日：2003-08-29

申请人： Eddie Miller ,  David Duckman ,  Jim Butler ,  Daming Jin ,  John Tang

发明人： Eddie Miller ,  David Duckman ,  Jim Butler ,  Daming Jin ,  John Tang

IPC分类号： G06F20060101 ,  G06F13/28 ,  G06F13/38

CPC分类号： G06F13/385 ,  G06F13/28

摘要： A method and system for allowing a host device (e.g., server) to perform programmed direct accesses to peripheral memory (e.g., flash) located on a peripheral device (e.g., HBA), without the assistance of a microprocessor located on the peripheral device. In a preferred embodiment, new host registers are implemented within controller circuitry of the peripheral device, the host registers being configured to be recognized by host software executed by host. The host device reads and writes to the host registers, which causes appropriate controller hardware to access the peripheral nonvolatile memory accordingly. By creating and implementing the new host registers, an enhanced controller is created that allows a host device to directly access peripheral memory, without peripheral processor assistance.

摘要翻译： 一种用于允许主机设备（例如，服务器）在位于外围设备上的微处理器的帮助下对位于外围设备（例如，HBA）上的外围存储器（例如，闪存）进行编程的直接访问的方法和系统。 在优选实施例中，新的主机寄存器被实现在外围设备的控制器电路内，主机寄存器被配置为由主机执行的主机软件识别。 主机设备读取和写入主机寄存器，这导致适当的控制器硬件相应地访问外设非易失性存储器。 通过创建和实现新的主机寄存器，创建一个增强的控制器，允许主机设备直接访问外围存储器，而无需外设处理器的帮助。