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公开(公告)号：US07091982B2
公开(公告)日：2006-08-15
申请号：US10846097
申请日：2004-05-14
申请人： Edward A. Hutchins , Brian K. Angell , Paul Kim
发明人： Edward A. Hutchins , Brian K. Angell , Paul Kim
CPC分类号： G06T15/005 , G06F9/3001 , G06F9/30025 , G06T1/20
摘要： A graphics processor is disclosed having a programmable Arithmetic Logic Unit (ALU) stage for processing pixel packets. Scalar arithmetic operations are performed in the ALUs to implement a graphics function.
摘要翻译： 公开了具有用于处理像素分组的可编程算术逻辑单元（ALU）级的图形处理器。 在ALU中执行标量算术运算以实现图形功能。
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2.发明授权System and method for a universal data write unit in a 3-D graphics pipeline including generic cache memories 有权用于包含通用高速缓存存储器的3-D图形管线中的通用数据写入单元的系统和方法公开(公告)号：US07724263B2
公开(公告)日：2010-05-25
申请号：US10846774
申请日：2004-05-14
申请人： Edward A. Hutchins , Paul Kim , Brian K. Angell
发明人： Edward A. Hutchins , Paul Kim , Brian K. Angell
CPC分类号： G06F12/0875 , G06T1/60 , G06T15/005
摘要： A system and method for a data write unit in a 3-D graphics pipeline including generic cache memories. Specifically, in one embodiment a data write unit includes a first memory, a plurality of cache memories and a data write circuit. The first memory receives a pixel packet associated with a pixel. The pixel packet includes data related to surface characteristics of the pixel. The plurality of cache memories is coupled to the first memory for storing pixel information associated with a plurality of surface characteristics of a plurality of pixels. Each of the plurality of cache memories is programmably associated with a designated surface characteristic. The data write circuit is coupled to the first a memory and the plurality of cache memories. The data write circuit is operable under program control to obtain designated portions of the pixel packet for storage into the plurality of cache memories.
摘要翻译： 一种用于包含通用高速缓冲存储器的3-D图形管线中的数据写入单元的系统和方法。 具体地，在一个实施例中，数据写入单元包括第一存储器，多个高速缓冲存储器和数据写入电路。 第一存储器接收与像素相关联的像素分组。 像素分组包括与像素的表面特性有关的数据。 多个高速缓冲存储器耦合到第一存储器，用于存储与多个像素的多个表面特性相关联的像素信息。 多个高速缓冲存储器中的每一个可编程地与指定的表面特性相关联。 数据写入电路耦合到第一个存储器和多个高速缓存存储器。 数据写入电路在程序控制下可操作以获得用于存储到多个高速缓冲存储器中的像素分组的指定部分。
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公开(公告)号：US07969446B2
公开(公告)日：2011-06-28
申请号：US11374947
申请日：2006-03-13
申请人： Edward A. Hutchins , Brian K. Angell , Paul Kim
发明人： Edward A. Hutchins , Brian K. Angell , Paul Kim
IPC分类号： G09G5/37
CPC分类号： G06T15/005 , G06F9/3001 , G06F9/30025 , G06T1/20
摘要： A graphics processor is disclosed having a programmable Arithmetic Logic Unit (ALU) stage for processing pixel packets. Scalar arithmetic operations are performed in the ALUs to implement a graphics function.
摘要翻译： 公开了具有用于处理像素分组的可编程算术逻辑单元（ALU）级的图形处理器。 在ALU中执行标量算术运算以实现图形功能。
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公开(公告)号：US08743142B1
公开(公告)日：2014-06-03
申请号：US10845986
申请日：2004-05-14
CPC分类号： G06T11/40 , G06T15/005 , G06T15/04 , G06T2200/28 , G06T2210/32
摘要： A present invention pixel processing system and method permit complicated three dimensional images to be rendered with shallow graphics pipelines including reduced gate counts and facilitates power conservation by utilizing a single unified data fetch stage (e.g., unified data fetch module) that retrieves a variety of different pixel surface attribute values (e.g., depth, color, and/or texture values) in a single stage. Different types of pixel surface attribute data (e.g., depth, color, texture) associated with multiple graphics processing functions (e.g., color blending, texture mapping, etc.) are retrieved in the single unified data fetch graphics pipeline stage. The pixel surface attribute values may be placed in corresponding variable fields of a pixel packet row. The pixel packet rows including the pixel surface attribute values are forwarded to downstream graphics pipeline stages (e.g., an arithmetic logic pipestage).
摘要翻译： 本发明的像素处理系统和方法允许使用包括减少的门数的浅图形管线来呈现复杂的三维图像，并且通过利用单个统一的数据提取阶段（例如，统一的数据获取模块）来简化功率节省，该统一数据获取阶段检索各种不同的 像素表面属性值（例如，深度，颜色和/或纹理值）。 在单个统一数据提取图形流水线阶段检索与多个图形处理功能（例如，颜色混合，纹理映射等）相关联的不同类型的像素表面属性数据（例如，深度，颜色，纹理）。 像素表面属性值可以被放置在像素分组行的对应的可变字段中。 包括像素表面属性值的像素分组行被转发到下游图形流水线级（例如，算术逻辑分支）。
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5.发明授权Method and system for implementing multiple high precision and low precision interpolators for a graphics pipeline 有权用于为图形管线实现多个高精度和低精度内插器的方法和系统公开(公告)号：US07079156B1
公开(公告)日：2006-07-18
申请号：US10845640
申请日：2004-05-14
IPC分类号： G09G5/00
CPC分类号： G06T15/005 , G06T11/40
摘要： A rasterizer stage configured to implement multiple interpolators for graphics pipeline. The rasterizer stage includes a plurality of simultaneously operable low precision interpolators for computing a first set of pixel parameters for pixels of a geometric primitive and a plurality of simultaneously operable high precision interpolators for computing a second set of pixel parameters for pixels of the geometric primitive. The rasterizer stage also includes an output mechanism coupled to the interpolators for routing computed pixel parameters into a memory array. Parameters may be programmably assigned to the interpolators and the results thereof may be programmably assigned to portions of a pixel packet.
摘要翻译： 光栅化器级配置为实现图形管线的多个插值器。 光栅化器级包括多个可同时操作的低精度内插器，用于计算几何图元的像素的第一组像素参数和用于计算几何图元的像素的第二组像素参数的多个可同时操作的高精度内插器。 光栅化器级还包括耦合到内插器的输出机构，用于将计算出的像素参数路由到存储器阵列中。 参数可以可编程地分配给内插器，并且其结果可以可编程地分配给像素分组的部分。
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6.发明申请Auto Software Configurable Register Address Space For Low Power Programmable Processor 审中-公开用于低功耗可编程处理器的自动软件可配置寄存器地址空间公开(公告)号：US20080204461A1
公开(公告)日：2008-08-28
申请号：US12115789
申请日：2008-05-06
IPC分类号： G06T1/20
CPC分类号： G06T15/005
摘要： A configurable graphics pipeline has more than one possible process flow of pixel packets through elements of the graphics pipeline. In one embodiment, a data packet triggers an element of the graphics pipeline to discover an identifier.
摘要翻译： 可配置的图形流水线通过图形流水线的元素具有多个可能的像素数据包流程。 在一个实施例中，数据分组触发图形流水线的元素以发现标识符。
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公开(公告)号：US20080117221A1
公开(公告)日：2008-05-22
申请号：US10845662
申请日：2004-05-14
IPC分类号： G06T1/20
CPC分类号： G06T15/40 , G06F9/3867 , G06F9/3869 , G06T15/005 , G06T2200/28
摘要： A pixel processing system and method which permits rendering of complicated three dimensional images using a shallow graphics pipeline including reduced gate counts and low power operation. Pixel packet information includes pixel surface attribute values retrieved in a single unified data fetch stage. A determination is made if the pixel packet information contributes to an image display presentation (e.g., a depth comparison of Z values may be performed). The pixel packet information processing is handled in accordance with results of the determining. The pixel surface attribute values and pixel packet information are removed from further processing if the pixel surface attribute values are occluded. In one exemplary implementation, the pixel packet includes a plurality of rows and the handling is coordinated for the plurality of rows. Any of a number of downstream pipestages may remove the occluded pixel information, and in response thereto, may notify a gatekeeper pipestage of the slack increase so that more pixels can be allowed into the pipeline.
摘要翻译： 一种像素处理系统和方法，其允许使用包括减少的门数和低功率操作的浅图形管线来呈现复杂的三维图像。 像素分组信息包括在单个统一数据获取阶段检索的像素表面属性值。 如果像素分组信息有助于图像显示呈现（例如，可以执行Z值的深度比较），则确定。 根据确定的结果处理像素分组信息处理。 如果像素表面属性值被遮挡，则像素表面属性值和像素分组信息从进一步处理中去除。 在一个示例性实现中，像素分组包括多个行，并且对于多个行来协调处理。 多个下游管道中的任何一个可以去除遮挡的像素信息，并且响应于此，可以通知网守管道的松弛增加，使得可以允许更多的像素进入流水线。
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8.发明授权Method and system for implementing multiple high precision and low precision interpolators for a graphics pipeline 有权用于为图形管线实现多个高精度和低精度内插器的方法和系统公开(公告)号：US08749576B2
公开(公告)日：2014-06-10
申请号：US11482669
申请日：2006-07-06
IPC分类号： G09G5/00
CPC分类号： G06T15/005 , G06T11/40
摘要： A rasterizer stage configured to implement multiple interpolators for graphics pipeline. The rasterizer stage includes a plurality of simultaneously operable low precision interpolators for computing a first set of pixel parameters for pixels of a geometric primitive and a plurality of simultaneously operable high precision interpolators for computing a second set of pixel parameters for pixels of the geometric primitive. The rasterizer stage also includes an output mechanism coupled to the interpolators for routing computed pixel parameters into a memory array. Parameters may be programmably assigned to the interpolators and the results thereof may be programmably assigned to portions of a pixel packet.
摘要翻译： 光栅化器级配置为实现图形管线的多个插值器。 光栅化器级包括多个可同时操作的低精度内插器，用于计算几何图元的像素的第一组像素参数和用于计算几何图元的像素的第二组像素参数的多个可同时操作的高精度内插器。 光栅化器级还包括耦合到内插器的输出机构，用于将计算出的像素参数路由到存储器阵列中。 参数可以可编程地分配给内插器，并且其结果可以可编程地分配给像素分组的部分。
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公开(公告)号：US08736620B2
公开(公告)日：2014-05-27
申请号：US10846201
申请日：2004-05-14
CPC分类号： G06T15/005
摘要： A present invention pixel processing system and method permit complicated three dimensional images to be rendered with shallow graphics pipelines including reduced gate counts and also facilitates power conservation. Pixel packet information includes pixel surface attribute values are retrieved in a single unified data fetch stage. At a data fetch pipestage a determination may be made if the pixel packet information contributes to an image display presentation (e.g., a depth comparison of Z values is performed determine if the pixel is occluded). A pixel packet status indicator (e.g., a kill bit) is set in the sideband portion of a pixel packet and the pixel packet is forwarded for processing in accordance with the pixel packet status indicator. The status indicator is a kill bit is set to prevent logic components from clocking information for a payload portion of the pixel packet if the status indicator indicates the pixel packet payload does not contribute to the image display presentation while continuing to clock pixel packet sideband information.
摘要翻译： 本发明的像素处理系统和方法允许使用包括减少的栅极数量的浅图形管线来呈现复杂的三维图像，并且还有助于功率节省。 像素分组信息包括像素表面属性值在单个统一数据获取阶段检索。 在数据提取管线处，可以确定像素分组信息是否有助于图像显示呈现（例如，执行Z值的深度比较来确定像素是否被遮挡）。 像素分组状态指示符（例如，杀死比特）被设置在像素分组的边带部分中，并且像素分组被转发以根据像素分组状态指示符进行处理。 如果状态指示符指示像素分组有效载荷对图像显示呈现不起作用，同时继续对像素分组边带信息进行时钟处理，则状态指示符是设置为防止逻辑组件针对像素分组的有效载荷部分的时钟信息。
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公开(公告)号：US08711155B2
公开(公告)日：2014-04-29
申请号：US10845662
申请日：2004-05-14
CPC分类号： G06T15/40 , G06F9/3867 , G06F9/3869 , G06T15/005 , G06T2200/28
摘要： A pixel processing system and method which permits rendering of complicated three dimensional images using a shallow graphics pipeline including reduced gate counts and low power operation. Pixel packet information includes pixel surface attribute values retrieved in a single unified data fetch stage. A determination is made if the pixel packet information contributes to an image display presentation (e.g., a depth comparison of Z values may be performed). The pixel packet information processing is handled in accordance with results of the determining. The pixel surface attribute values and pixel packet information are removed from further processing if the pixel surface attribute values are occluded. In one exemplary implementation, the pixel packet includes a plurality of rows and the handling is coordinated for the plurality of rows. Any of a number of downstream pipestages may remove the occluded pixel information, and in response thereto, may notify a gatekeeper pipestage of the slack increase so that more pixels can be allowed into the pipeline.
摘要翻译： 一种像素处理系统和方法，其允许使用包括减少的门数和低功率操作的浅图形管线来呈现复杂的三维图像。 像素分组信息包括在单个统一数据获取阶段检索的像素表面属性值。 如果像素分组信息有助于图像显示呈现（例如，可以执行Z值的深度比较），则确定。 根据确定的结果处理像素分组信息处理。 如果像素表面属性值被遮挡，则像素表面属性值和像素分组信息从进一步处理中去除。 在一个示例性实现中，像素分组包括多个行，并且对于多个行来协调处理。 多个下游管道中的任何一个可以去除遮挡的像素信息，并且响应于此，可以通知网守管道的松弛增加，使得可以允许更多的像素进入流水线。
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