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    METHOD, SYSTEM, COMPUTER PROGRAM PRODUCT, AND HARDWARE PRODUCT FOR IMPLEMENTING RESULT FORWARDING BETWEEN DIFFERENTLY SIZED OPERANDS IN A SUPERSCALAR PROCESSOR
    1.
    发明申请
    METHOD, SYSTEM, COMPUTER PROGRAM PRODUCT, AND HARDWARE PRODUCT FOR IMPLEMENTING RESULT FORWARDING BETWEEN DIFFERENTLY SIZED OPERANDS IN A SUPERSCALAR PROCESSOR 失效
    方法，系统，计算机程序产品和用于在超级处理器中执行不同尺寸操作之前的结果的硬件产品

    公开(公告)号：US20090240922A1

    公开(公告)日：2009-09-24

    申请号：US12051792

    申请日：2008-03-19

    申请人： David S. Hutton ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  Christopher A. Krygowski ,  Edward T. Malley ,  Jeffrey S. Plate ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum ,  Timothy J. Slegel

    发明人： David S. Hutton ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  Christopher A. Krygowski ,  Edward T. Malley ,  Jeffrey S. Plate ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum ,  Timothy J. Slegel

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3016 ,  G06F9/30036 ,  G06F9/3828

    摘要： Result and operand forwarding is provided between differently sized operands in a superscalar processor by grouping a first set of instructions for operand forwarding, and grouping a second set of instructions for result forwarding, the first set of instructions comprising a first source instruction having a first operand and a first dependent instruction having a second operand, the first dependent instruction depending from the first source instruction; the second set of instructions comprising a second source instruction having a third operand and a second dependent instruction having a fourth operand, the second dependent instruction depending from the second source instruction, performing operand forwarding by forwarding the first operand, either whole or in part, as it is being read to the first dependent instruction prior to execution; performing result forwarding by forwarding a result of the second source instruction, either whole or in part, to the second dependent instruction, after execution; wherein the operand forwarding is performed by executing the first source instruction together with the first dependent instruction; and wherein the result forwarding is performed by executing the second source instruction together with the second dependent instruction.

    摘要翻译： 通过对用于操作数转发的第一组指令进行分组，以及对用于结果转发的第二组指令进行分组，在超标量处理器中的不同大小的操作数之间提供结果和操作数转发，所述第一组指令包括具有第一操作数的第一源指令 以及具有第二操作数的第一依赖指令，所述第一依赖指令取决于所述第一源指令; 所述第二组指令包括具有第三操作数和第二从属指令的第二源指令，所述第三操作数和第二从属指令具有第四操作数，所述第二依赖指令取决于所述第二源指令，通过转发所述第一操作数全部或部分地执行操作数转发， 因为它在执行之前被读取到第一个依赖指令; 执行结果转发，将第二源指令的结果全部或部分转发到第二依赖指令; 其中通过与第一依赖指令一起执行第一源指令来执行操作数转发; 并且其中通过与第二从属指令一起执行第二源指令来执行结果转发。

    Operand and result forwarding between differently sized operands in a superscalar processor
    3.
    发明授权
    Operand and result forwarding between differently sized operands in a superscalar processor 失效
    操作数和结果在超标量处理器中的不同大小的操作数之间转发

    公开(公告)号：US07921279B2

    公开(公告)日：2011-04-05

    申请号：US12051792

    申请日：2008-03-19

    申请人： David S. Hutton ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  Christopher A. Krygowski ,  Edward T. Malley ,  Jeffrey S. Plate ,  John G. Rell, Jr. ,  Chung-Lung Kevin Shum ,  Timothy J. Slegel

    发明人： David S. Hutton ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  Christopher A. Krygowski ,  Edward T. Malley ,  Jeffrey S. Plate ,  John G. Rell, Jr. ,  Chung-Lung Kevin Shum ,  Timothy J. Slegel

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3016 ,  G06F9/30036 ,  G06F9/3828

    摘要： Result and operand forwarding is provided between differently sized operands in a superscalar processor by grouping a first set of instructions for operand forwarding, and grouping a second set of instructions for result forwarding, the first set of instructions comprising a first source instruction having a first operand and a first dependent instruction having a second operand, the first dependent instruction depending from the first source instruction; the second set of instructions comprising a second source instruction having a third operand and a second dependent instruction having a fourth operand, the second dependent instruction depending from the second source instruction, performing operand forwarding by forwarding the first operand, either whole or in part, as it is being read to the first dependent instruction prior to execution; performing result forwarding by forwarding a result of the second source instruction, either whole or in part, to the second dependent instruction, after execution; wherein the operand forwarding is performed by executing the first source instruction together with the first dependent instruction; and wherein the result forwarding is performed by executing the second source instruction together with the second dependent instruction.

    摘要翻译： 通过对用于操作数转发的第一组指令进行分组，以及对用于结果转发的第二组指令进行分组，在超标量处理器中的不同大小的操作数之间提供结果和操作数转发，所述第一组指令包括具有第一操作数的第一源指令 以及具有第二操作数的第一依赖指令，所述第一依赖指令取决于所述第一源指令; 所述第二组指令包括具有第三操作数和第二从属指令的第二源指令，所述第三操作数和第二从属指令具有第四操作数，所述第二依赖指令取决于所述第二源指令，通过转发所述第一操作数全部或部分地执行操作数转发， 因为它在执行之前被读取到第一个依赖指令; 执行结果转发，将第二源指令的结果全部或部分转发到第二依赖指令; 其中通过与第一依赖指令一起执行第一源指令来执行操作数转发; 并且其中通过与第二从属指令一起执行第二源指令来执行结果转发。

    Recycling long multi-operand instructions
    5.
    发明授权
    Recycling long multi-operand instructions 失效
    回收长操作数指令

    公开(公告)号：US07962726B2

    公开(公告)日：2011-06-14

    申请号：US12051215

    申请日：2008-03-19

    申请人： Edward T. Malley ,  Khary J. Alexander ,  Fadi Y. Busaba ,  Vimal M. Kapadia ,  Jeffrey S. Plate ,  John G. Rell, Jr. ,  Chung-Lung Kevin Shum

    发明人： Edward T. Malley ,  Khary J. Alexander ,  Fadi Y. Busaba ,  Vimal M. Kapadia ,  Jeffrey S. Plate ,  John G. Rell, Jr. ,  Chung-Lung Kevin Shum

    IPC分类号： G06F9/00 ,  G06F9/44

    CPC分类号： G06F9/30065 ,  G06F9/3832

    摘要： A pipelined microprocessor configured for long operand instructions is disclosed. The microprocessor includes a memory unit and a load-store unit. The load store unit is coupled to the memory unit and includes a data formatter receiving information from the memory unit and including an operand selector and a shift register portion. The microprocessor also includes an execution unit coupled to the load-store unit and receiving operand information there from. The execution unit includes output latches coupled to a storage location within the execution unit for storing output information from the execution unit.

    摘要翻译： 公开了配置用于长操作数指令的流水线微处理器。 微处理器包括存储单元和加载存储单元。 加载存储单元耦合到存储器单元，并且包括从存储器单元接收信息并包括操作数选择器和移位寄存器部分的数据格式化器。 微处理器还包括耦合到加载存储单元并从其接收操作数信息的执行单元。 执行单元包括耦合到执行单元内的存储位置的输出锁存器，用于存储来自执行单元的输出信息。

    Modular binary multiplier for signed and unsigned operands of variable widths
    6.
    发明授权
    Modular binary multiplier for signed and unsigned operands of variable widths 有权
    具有可变宽度的有符号和无符号操作数的模块二进制乘法器

    公开(公告)号：US07490121B2

    公开(公告)日：2009-02-10

    申请号：US11749239

    申请日：2007-05-16

    申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  David S. Hutton ,  Christopher A. Krygowski ,  John G. Rell, Jr. ,  Sheryll H. Veneracion

    发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  David S. Hutton ,  Christopher A. Krygowski ,  John G. Rell, Jr. ,  Sheryll H. Veneracion

    IPC分类号： G06F7/52

    CPC分类号： G06F7/5324 ,  G06F7/5332 ,  G06F9/30014 ,  G06F2207/3816

    摘要： A method of implementing binary multiplication in a processing device includes obtaining a multiplicand and a multiplier from a storage device; in the event the multiplier is larger than a selected length, partitioning the multiplier into a plurality of multiplier subgroups; in the event the multiplicand is larger than a selected length, partitioning the multiplicand into a plurality of multiplicand subgroups and at least one of zeroing out of unused bits of the multiplicand subgroup and sign-extending a smaller portion of the multiplicand subgroup; establishing a plurality of multiplicand multiples based on at least one of a selected multiplicand subgroup of the plurality of multiplicand subgroups and the multiplicand; selecting one or more of the multiplicand multiples of the plurality of multiplicand multiples based on the each multiplier subgroup of the plurality of multiplier subgroups; and generating a first modular product based on the selected multiplicand multiples.

    摘要翻译： 在处理设备中实现二进制乘法的方法包括从存储设备获取乘法器和乘法器; 在乘数大于选定长度的情况下，将乘法器分成多个乘法器子组; 在所述被乘数大于所选择的长度的情况下，将所述被乘数划分为多个被乘数的子组和被乘数子组的未使用的比特中的至少一个，并对被乘数子组的较小部分进行符号扩展; 基于所述多个被乘数子组和被乘数中的所选择的被乘数子群中的至少一个，建立多个被乘数; 基于所述多个乘法器子组中的每个乘法器子组来选择所述多个被乘数中的一个或多个被乘数; 以及基于所选择的被乘数生成第一模块化产品。

    RECYCLING LONG MULTI-OPERAND INSTRUCTIONS
    7.
    发明申请
    RECYCLING LONG MULTI-OPERAND INSTRUCTIONS 失效
    回收长时间的多操作指令

    公开(公告)号：US20090240914A1

    公开(公告)日：2009-09-24

    申请号：US12051215

    申请日：2008-03-19

    申请人： Edward T. Malley ,  Khary J. Alexander ,  Fadi Y. Busaba ,  Vimal M. Kapadia ,  Jeffrey S. Plate ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum

    发明人： Edward T. Malley ,  Khary J. Alexander ,  Fadi Y. Busaba ,  Vimal M. Kapadia ,  Jeffrey S. Plate ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum

    IPC分类号： G06F9/38

    CPC分类号： G06F9/30065 ,  G06F9/3832

    摘要： A pipelined microprocessor configured for long operand instructions is disclosed. The microprocessor includes a memory unit and a load-store unit. The load store unit is coupled to the memory unit and includes a data formatter receiving information from the memory unit and including an operand selector and a shift register portion. The microprocessor also includes an execution unit coupled to the load-store unit and receiving operand information there from. The execution unit includes output latches coupled to a storage location within the execution unit for storing output information from the execution unit.

    摘要翻译： 公开了配置用于长操作数指令的流水线微处理器。 微处理器包括存储单元和加载存储单元。 加载存储单元耦合到存储器单元，并且包括从存储器单元接收信息并包括操作数选择器和移位寄存器部分的数据格式化器。 微处理器还包括耦合到加载存储单元并从其接收操作数信息的执行单元。 执行单元包括耦合到执行单元内的存储位置的输出锁存器，用于存储来自执行单元的输出信息。

    Modular binary multiplier for signed and unsigned operands of variable widths
    8.
    发明授权
    Modular binary multiplier for signed and unsigned operands of variable widths 有权
    具有可变宽度的有符号和无符号操作数的模块二进制乘法器

    公开(公告)号：US07853635B2

    公开(公告)日：2010-12-14

    申请号：US11749224

    申请日：2007-05-16

    申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  David S. Hutton ,  Christopher A. Krygowski ,  John G. Rell, Jr. ,  Sheryll H. Veneracion

    发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  David S. Hutton ,  Christopher A. Krygowski ,  John G. Rell, Jr. ,  Sheryll H. Veneracion

    IPC分类号： G06F7/38 ,  G06F7/52

    CPC分类号： G06F7/5324 ,  G06F7/5332 ,  G06F9/30014 ,  G06F2207/3816

    摘要： A system for binary multiplication in a superscalar processor includes a first pipeline, an execution unit, and a first multiplexer; a first rotator in communication with one register of the first pipeline and the execution unit; and a leading zero detection register in communication with the execution unit and another register of the first pipeline; a second pipeline, a second execution unit, and a second multiplexer; a rotator in communication with one register of the second pipeline and the second execution unit; and a leading zero detection register in communication with the second execution unit and another register of the first pipeline; and a third pipeline, a binary multiplier in communication with a pair registers of the third pipeline; a general register; an operand buffer for obtaining first and second operands; and a bus for communication between the pipelines, the general register and the operand buffer.

    摘要翻译： 超标量处理器中的二进制乘法系统包括第一流水线，执行单元和第一多路复用器; 与第一流水线和执行单元的一个寄存器通信的第一旋转器; 以及与执行单元和第一管道的另一个寄存器通信的前导零检测寄存器; 第二管线，第二执行单元和第二多路复用器; 与所述第二管线的一个寄存器和所述第二执行单元通信的转动器; 以及与第二执行单元和第一管道的另一个寄存器通信的前导零检测寄存器; 以及第三管线，与所述第三管道的对寄存器通信的二进制乘法器; 一般登记册; 用于获得第一和第二操作数的操作数缓冲器; 和一条总线，用于管道，通用寄存器和操作数缓冲区之间的通信。

    Modular binary multiplier for signed and unsigned operands of variable widths
    9.
    发明授权
    Modular binary multiplier for signed and unsigned operands of variable widths 有权
    具有可变宽度的有符号和无符号操作数的模块二进制乘法器

    公开(公告)号：US07266580B2

    公开(公告)日：2007-09-04

    申请号：US10435976

    申请日：2003-05-12

    申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  David S. Hutton ,  Christopher A. Krygowski ,  John G. Rell, Jr. ,  Sheryll H. Veneracion

    发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  David S. Hutton ,  Christopher A. Krygowski ,  John G. Rell, Jr. ,  Sheryll H. Veneracion

    IPC分类号： G06F7/52

    CPC分类号： G06F7/5324 ,  G06F7/5332 ,  G06F9/30014 ,  G06F2207/3816

    摘要： A method and apparatuses for performing binary multiplication on signed and unsigned operands of various lengths is discussed herein. It is a concept that may be split into two parts, the first of which is the multiplication hardware itself, a compact, less than-full sized multiplier employing Booth or other type of recoding methods upon the multiplier to reduce the number of partial products per scan, and implemented in such a manner so that a multiplication operation with large operands may be broken into subgroups of operations that will fit into this mid-sized multiplier whose results, here called modular products, may be knitted back together to form a correct, final product. The second part of the concept is the supporting hardware used to separate the operands into subgroups and input the data and control signals to the multiplier, and the algorithms and apparatuses used to align and combine the modular products properly to obtain the final product. These algorithms used to obtain a result as specified by the operation may be as varied as the supporting hardware with which the multiplier may be used, making this multiplier a very flexible and powerful design.

    摘要翻译： 本文中讨论了用于对具有各种长度的有符号和无符号操作数进行二进制乘法的方法和装置。 这是一个概念，可以分为两部分，第一部分是乘法硬件本身，紧凑型，小于满量程的乘法器，在乘数上使用Booth或其他类型的重新编码方法，以减少每个部分产品的数量 扫描和实现，使得具有大操作数的乘法运算可以被分解成适合于该中型乘法器的操作子组，其结果（这里称为模块化产品）可以针织在一起以形成正确的， 完成品。 该概念的第二部分是用于将操作数分成子组并将数据和控制信号输入到乘法器的支持硬件，以及用于对准和组合模块化产品以获得最终产品的算法和装置。 用于获得由操作指定的结果的这些算法可以与可以使用乘法器的支持硬件一样变化，使得该乘法器是非常灵活和强大的设计。

    METHOD, COMPUTER PROGRAM PRODUCT, AND HARDWARE PRODUCT FOR ELIMINATING OR REDUCING OPERAND LINE CROSSING PENALTY
    10.
    发明申请
    METHOD, COMPUTER PROGRAM PRODUCT, AND HARDWARE PRODUCT FOR ELIMINATING OR REDUCING OPERAND LINE CROSSING PENALTY 有权
    方法，计算机程序产品和用于消除或减少操作线交叉罚款的五金产品

    公开(公告)号：US20090240918A1

    公开(公告)日：2009-09-24

    申请号：US12051296

    申请日：2008-03-19

    申请人： Vimal M. Kapadia ,  Fadi Y. Busaba ,  Edward T. Malley ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum

    发明人： Vimal M. Kapadia ,  Fadi Y. Busaba ,  Edward T. Malley ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3824

    摘要： Eliminating or reducing an operand line crossing penalty by performing an initial fetch for an operand from a data cache of a processor. The initial fetch is performed by allowing or permitting the initial fetch to occur unaligned with reference to a quadword boundary. A plurality of subsequent fetches for a corresponding plurality of operands from the data cache are performed wherein each of the plurality of subsequent fetches is aligned to any of a plurality of quadword boundaries to prevent each of a plurality of individual fetch requests from spanning a plurality of lines in the data cache. A steady stream of data is maintained by placing an operand buffer at an output of the data cache to store and merge data from the initial fetch and the plurality of subsequent fetches, and to return the stored and merged data to the processor.

    摘要翻译： 通过从处理器的数据高速缓存中执行对操作数的初始提取来消除或减少操作数线路交叉处罚。 初始提取是通过允许或允许以参考四字边界未对齐的方式发生初始提取而执行的。 执行用于来自数据高速缓存的相应多个操作数的多个后续提取，其中多个后续提取中的每一个与多个四字边界中的任何一个对齐，以防止多个单独提取请求中的每一个跨越多个 数据缓存中的行。 通过在数据高速缓存的输出处放置操作数缓冲器来存储和合并来自初始提取和多个后续提取的数据并将存储和合并的数据返回到处理器来维持稳定的数据流。