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1.发明授权Methods and apparatus for scalable array processor interrupt detection and response 失效用于可扩展阵列处理器中断检测和响应的方法和装置公开(公告)号：US08751772B2
公开(公告)日：2014-06-10
申请号：US13916877
申请日：2013-06-13
IPC分类号： G06F11/27
CPC分类号： G06F9/3865 , G06F9/30058 , G06F9/3861 , G06F9/4812 , G06F11/27 , G06F13/26 , Y02D10/14 , Y02D10/24
摘要： Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debug interrupts and a dynamic debut monitor mechanism.
摘要翻译： 描述了可扩展流水线阵列处理器环境中的中断检测和响应的硬件和软件技术。 利用这些技术，可以在包含多个处理元件和分布式存储器和寄存器文件的高度并行的可扩展流水线阵列处理中维持具有中断的顺序程序执行模型。 当发生中断时，接口信号提供给所有PE，以支持每个PE中的独立中断操作，取决于中断前的本地PE指令序列。 支持处理/元件异常中断，并为需要实时信号处理的嵌入式系统提供低延迟中断处理。 此外，使用分层中断结构，允许使用调试中断的通用调试方法和动态登场监视器机制。
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2.发明授权Methods and apparatus for scalable array processor interrupt detection and response 失效用于可扩展阵列处理器中断检测和响应的方法和装置公开(公告)号：US08489858B2
公开(公告)日：2013-07-16
申请号：US13417490
申请日：2012-03-12
IPC分类号： G06F15/00
CPC分类号： G06F9/3865 , G06F9/30058 , G06F9/3861 , G06F9/4812 , G06F11/27 , G06F13/26 , Y02D10/14 , Y02D10/24
摘要： Hardware and software techniques for interrupt detection and response are provided in a scalable pipelined array processor environment. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debug interrupts and a dynamic debug monitor mechanism.
摘要翻译： 用于中断检测和响应的硬件和软件技术在可扩展的流水线阵列处理器环境中提供。 利用这些技术，可以在包含多个处理元件和分布式存储器和寄存器文件的高度并行的可扩展流水线阵列处理中维持具有中断的顺序程序执行模型。 当发生中断时，接口信号提供给所有PE，以支持每个PE中的独立中断操作，取决于中断前的本地PE指令序列。 支持处理/元件异常中断，并为需要实时信号处理的嵌入式系统提供低延迟中断处理。 此外，使用分层中断结构，允许使用调试中断的通用调试方法和动态调试监视机制。
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3.发明申请Methods and Apparatus for Adapting Pipeline Stage Latency Based on Instruction Type 有权基于指令类型适应流水线延迟的方法与装置公开(公告)号：US20100318775A1
公开(公告)日：2010-12-16
申请号：US12861896
申请日：2010-08-24
IPC分类号： G06F9/38
CPC分类号： G06F9/30079 , G06F9/30145 , G06F9/3869 , G06F9/3885
摘要： Processor pipeline controlling techniques are described which take advantage of the variation in critical path lengths of different instructions to achieve increased performance. By examining a processor's instruction set and execution unit implementation's critical timing paths, instructions are classified into speed classes. Based on these speed classes, one pipeline is presented where hold signals are used to dynamically control the pipeline based on the instruction class in execution. An alternative pipeline supporting multiple classes of instructions is presented where the pipeline clocking is dynamically changed as a result of decoded instruction class signals. A single pass synthesis methodology for multi-class execution stage logic is also described. For dynamic class variable pipeline processors, the mix of instructions can have a great effect on processor performance and power utilization since both can vary by the program mix of instruction classes. Application code can be given new degrees of optimization freedom where instruction class and the mix of instructions can be chosen based on performance and power requirements.
摘要翻译： 描述了处理器流水线控制技术，其利用不同指令的关键路径长度的变化来实现增加的性能。 通过检查处理器的指令集和执行单元实现的关键时序路径，指令被分为速度等级。 基于这些速度等级，提出了一个管道，其中使用保持信号来基于执行中的指令类来动态地控制流水线。 提出了支持多类指令的替代流水线，其中流水线时钟作为解码指令类信号的结果动态地改变。 还描述了用于多类执行级逻辑的单程合成方法。 对于动态类变量流水线处理器，指令的混合可以对处理器性能和功率利用率产生很大的影响，因为它们可以根据指令类的程序组合而变化。 应用代码可以给出新的优化自由度，其中可以基于性能和功率要求来选择指令类和指令混合。
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公开(公告)号：US09329866B2
公开(公告)日：2016-05-03
申请号：US13780746
申请日：2013-02-28
CPC分类号： G06F9/30079 , G06F9/30145 , G06F9/3869 , G06F9/3885
摘要： Processor pipeline controlling techniques are described which take advantage of the variation in critical path lengths of different instructions to achieve increased performance. By examining a processor's instruction set and execution unit implementation's critical timing paths, instructions are classified into speed classes. Based on these speed classes, one pipeline is presented where hold signals are used to dynamically control the pipeline based on the instruction class in execution. An alternative pipeline supporting multiple classes of instructions is presented where the pipeline clocking is dynamically changed as a result of decoded instruction class signals. A single pass synthesis methodology for multi-class execution stage logic is also described. For dynamic class variable pipeline processors, the mix of instructions can have a great effect on processor performance and power utilization since both can vary by the program mix of instruction classes. Application code can be given new degrees of optimization freedom where instruction class and the mix of instructions can be chosen based on performance and power requirements.
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5.发明申请Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response 审中-公开用于可扩展阵列处理器中断检测和响应的方法和装置公开(公告)号：US20140237215A1
公开(公告)日：2014-08-21
申请号：US14264263
申请日：2014-04-29
IPC分类号： G06F9/38
CPC分类号： G06F9/3865 , G06F9/30058 , G06F9/3861 , G06F9/4812 , G06F11/27 , G06F13/26 , Y02D10/14 , Y02D10/24
摘要： Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism.
摘要翻译： 描述了可扩展流水线阵列处理器环境中的中断检测和响应的硬件和软件技术。 利用这些技术，可以在包含多个处理元件和分布式存储器和寄存器文件的高度并行的可扩展流水线阵列处理中维持具有中断的顺序程序执行模型。 当发生中断时，接口信号提供给所有PE，以支持每个PE中的独立中断操作，取决于中断前的本地PE指令序列。 支持处理/元件异常中断，并为需要实时信号处理的嵌入式系统提供低延迟中断处理。 此外，使用分层中断结构，允许使用初次中断的通用调试方法和动态登场监视机制。
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公开(公告)号：US08397000B2
公开(公告)日：2013-03-12
申请号：US13611969
申请日：2012-09-12
申请人： Gerald George Pechanek , David Strube , Edwin Franklin Barry , Charles W. Kurak, Jr. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
发明人： Gerald George Pechanek , David Strube , Edwin Franklin Barry , Charles W. Kurak, Jr. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
CPC分类号： G06F15/82 , G06F9/30145 , G06F11/263 , Y10S707/99943
摘要： Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.
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7.发明授权Methods and apparatus for scalable array processor interrupt detection and response 有权用于可扩展阵列处理器中断检测和响应的方法和装置公开(公告)号：US07386710B2
公开(公告)日：2008-06-10
申请号：US10931751
申请日：2004-09-01
CPC分类号： G06F9/3865 , G06F9/30058 , G06F9/3861 , G06F9/4812 , G06F11/27 , G06F13/26 , Y02D10/14 , Y02D10/24
摘要： Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements (PEs) and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debug interrupts and a dynamic debug monitor mechanism.
摘要翻译： 描述了可扩展流水线阵列处理器环境中的中断检测和响应的硬件和软件技术。 利用这些技术，可以在包含多个处理元件（PE）和分布式存储器和寄存器文件的高度并行的可扩展流水线阵列处理中维持具有中断的顺序程序执行模型。 当发生中断时，接口信号提供给所有PE，以支持每个PE中的独立中断操作，取决于中断前的本地PE指令序列。 支持处理/元件异常中断，并为需要实时信号处理的嵌入式系统提供低延迟中断处理。 此外，使用分层中断结构，允许使用调试中断的通用调试方法和动态调试监视机制。
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8.发明授权Cascaded event detection modules for generating combined events interrupt for processor action 失效用于生成组合事件的级联事件检测模块用于处理器动作中断公开(公告)号：US07058790B2
公开(公告)日：2006-06-06
申请号：US10786604
申请日：2004-02-25
IPC分类号： G06F11/30
CPC分类号： G06F9/30054 , G06F9/30101 , G06F9/30112 , G06F9/325
摘要： An eventpoint chaining apparatus for generalized event detection and action specification in a processing environment is described. In one aspect, the eventpoint chaining apparatus includes a first processor which has a programmable eventpoint module with an input trigger (InTrig) input. The first processing element detects an occurrence of a first processor event (p-event) and produces an OutTrigger (OT) signal. The eventpoint chaining apparatus also includes a second processor which has a programmable eventpoint module with an input trigger (InTrig) input which receives the OT signal from the first processing element. The second processing element detects an occurrence of a second p-event and produces, in response to the OT signal received from the first processing element and the detection of a second p-event, an eventpoint (EP) interrupt signal. The eventpoint chaining apparatus also includes a sequence processor interrupt control unit for receiving the EP interrupt signals indicating the occurrence of both the first and second p-events and causing a p-action in response to the occurrence of both the first and second p-events.
摘要翻译： 描述用于处理环境中的广义事件检测和动作规范的事件点链接装置。 一方面，事件点链接装置包括具有可输入触发（InTrig）输入的可编程事件点模块的第一处理器。 第一处理元件检测出第一处理器事件（p事件）的发生并产生OutTrigger（OT）信号。 事件点链接装置还包括具有可编程事件点模块的第二处理器，该可编程事件点模块具有从第一处理元件接收OT信号的输入触发（InTrig）输入。 第二处理元件检测第二p事件的发生，并且响应于从第一处理元件接收的OT信号和第二p事件的检测，产生事件点（EP）中断信号。 事件点链接装置还包括序列处理器中断控制单元，用于接收表示第一和第二p事件的发生的EP中断信号，并且响应于第一和第二p事件的发生而引起p动作 。
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9.发明授权Methods and apparatus for scalable array processor interrupt detection and response 有权用于可扩展阵列处理器中断检测和响应的方法和装置公开(公告)号：US09158547B2
公开(公告)日：2015-10-13
申请号：US14264263
申请日：2014-04-29
CPC分类号： G06F9/3865 , G06F9/30058 , G06F9/3861 , G06F9/4812 , G06F11/27 , G06F13/26 , Y02D10/14 , Y02D10/24
摘要： Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism.
摘要翻译： 描述了可扩展流水线阵列处理器环境中的中断检测和响应的硬件和软件技术。 利用这些技术，可以在包含多个处理元件和分布式存储器和寄存器文件的高度并行的可扩展流水线阵列处理中维持具有中断的顺序程序执行模型。 当发生中断时，接口信号提供给所有PE，以支持每个PE中的独立中断操作，取决于中断前的本地PE指令序列。 支持处理/元件异常中断，并为需要实时信号处理的嵌入式系统提供低延迟中断处理。 此外，使用分层中断结构，允许使用初次中断的通用调试方法和动态登场监视机制。
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10.发明申请Methods and Apparatus for Adapting Pipeline Stage Latency Based on Instruction Type 审中-公开基于指令类型适应流水线延迟的方法与装置公开(公告)号：US20140075157A1
公开(公告)日：2014-03-13
申请号：US13780746
申请日：2013-02-28
IPC分类号： G06F9/30
CPC分类号： G06F9/30079 , G06F9/30145 , G06F9/3869 , G06F9/3885
摘要： Processor pipeline controlling techniques are described which take advantage of the variation in critical path lengths of different instructions to achieve increased performance. By examining a processor's instruction set and execution unit implementation's critical timing paths, instructions are classified into speed classes. Based on these speed classes, one pipeline is presented where hold signals are used to dynamically control the pipeline based on the instruction class in execution. An alternative pipeline supporting multiple classes of instructions is presented where the pipeline clocking is dynamically changed as a result of decoded instruction class signals. A single pass synthesis methodology for multi-class execution stage logic is also described. For dynamic class variable pipeline processors, the mix of instructions can have a great effect on processor performance and power utilization since both can vary by the program mix of instruction classes. Application code can be given new degrees of optimization freedom where instruction class and the mix of instructions can be chosen based on performance and power requirements.
摘要翻译： 描述了处理器流水线控制技术，其利用不同指令的关键路径长度的变化来实现增加的性能。 通过检查处理器的指令集和执行单元实现的关键时序路径，指令被分为速度等级。 基于这些速度等级，提出了一个管道，其中使用保持信号来基于执行中的指令类来动态地控制流水线。 提出了支持多类指令的替代流水线，其中流水线时钟作为解码指令类信号的结果动态地改变。 还描述了用于多类执行级逻辑的单程合成方法。 对于动态类变量流水线处理器，指令的混合可以对处理器性能和功率利用率产生很大的影响，因为它们可以根据指令类的程序组合而变化。 应用代码可以给出新的优化自由度，其中可以基于性能和功率要求来选择指令类和指令混合。
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