公开(公告)号：US07266620B1

公开(公告)日：2007-09-04

申请号：US10797726

申请日：2004-03-10

申请人： Gerald George Pechanek ,  David Strube ,  Edwin Franklin Barry ,  Charles W. Kurak, Jr. ,  Carl Donald Busboom ,  Dale Edward Schneider ,  Nikos P. Pitsianis ,  Grayson Morris ,  Edward A. Wolff ,  Patrick R. Marchand ,  Ricardo E. Rodriguez ,  Marco C. Jacobs

发明人： Gerald George Pechanek ,  David Strube ,  Edwin Franklin Barry ,  Charles W. Kurak, Jr. ,  Carl Donald Busboom ,  Dale Edward Schneider ,  Nikos P. Pitsianis ,  Grayson Morris ,  Edward A. Wolff ,  Patrick R. Marchand ,  Ricardo E. Rodriguez ,  Marco C. Jacobs

IPC分类号： G06F13/28 ,  G06F13/00

CPC分类号： G06F15/82 ,  G06F9/30145 ,  G06F11/263 ,  Y10S707/99943

摘要： A system core having an internal memory which transfers data from an external device to the internal memory is described. To this end, the system core includes a processor, a direct memory access (DMA) controller, an instruction memory and a plurality of memories. The instruction memory contains processor instructions and DMA instructions. The DMA controller fetches DMA instructions from the instruction memory. The DMA controller executes the fetched DMA instructions and thus populates the plurality of memories with data from the external device. The processor then operates on the data found in the populated memories.

摘要翻译： 描述具有将数据从外部设备传送到内部存储器的内部存储器的系统核心。 为此，系统核心包括处理器，直接存储器访问（DMA）控制器，指令存储器和多个存储器。 指令存储器包含处理器指令和DMA指令。 DMA控制器从指令存储器中获取DMA指令。 DMA控制器执行所提取的DMA指令，并且由此来自外部设备的数据填充多个存储器。 然后，处理器对在填充的存储器中找到的数据进行操作。

公开(公告)号：US08296479B2

公开(公告)日：2012-10-23

申请号：US13344339

申请日：2012-01-05

申请人： Gerald George Pechanek ,  David Strube ,  Edwin Franklin Barry ,  Charles W. Kurak, Jr. ,  Carl Donald Busboom ,  Dale Edward Schneider ,  Nikos P. Pitsianis ,  Grayson Morris ,  Edward A. Wolff ,  Patrick R. Marchand ,  Ricardo E. Rodriguez ,  Marco C. Jacobs

发明人： Gerald George Pechanek ,  David Strube ,  Edwin Franklin Barry ,  Charles W. Kurak, Jr. ,  Carl Donald Busboom ,  Dale Edward Schneider ,  Nikos P. Pitsianis ,  Grayson Morris ,  Edward A. Wolff ,  Patrick R. Marchand ,  Ricardo E. Rodriguez ,  Marco C. Jacobs

IPC分类号： G06F13/36 ,  G06F13/00

CPC分类号： G06F15/82 ,  G06F9/30145 ,  G06F11/263 ,  Y10S707/99943

摘要： Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.

摘要翻译： 这里描述了使用歧管阵列（ManArray）架构和指令语法的高成本有效和高效的实现的细节。 该方法的各个方面包括语法的规律性，指示集可以以数据库形式表示的相对容易程度，可以创建工具的就绪能力，即时生成自检代码和参数化测试用例。 可以很容易地映射参数化，并显着简化系统维护。

公开(公告)号：US08397000B2

公开(公告)日：2013-03-12

申请号：US13611969

申请日：2012-09-12

申请人： Gerald George Pechanek ,  David Strube ,  Edwin Franklin Barry ,  Charles W. Kurak, Jr. ,  Carl Donald Busboom ,  Dale Edward Schneider ,  Nikos P. Pitsianis ,  Grayson Morris ,  Edward A. Wolff ,  Patrick R. Marchand ,  Ricardo E. Rodriguez ,  Marco C. Jacobs

发明人： Gerald George Pechanek ,  David Strube ,  Edwin Franklin Barry ,  Charles W. Kurak, Jr. ,  Carl Donald Busboom ,  Dale Edward Schneider ,  Nikos P. Pitsianis ,  Grayson Morris ,  Edward A. Wolff ,  Patrick R. Marchand ,  Ricardo E. Rodriguez ,  Marco C. Jacobs

IPC分类号： G06F13/36 ,  G06F13/00

CPC分类号： G06F15/82 ,  G06F9/30145 ,  G06F11/263 ,  Y10S707/99943

摘要： Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.

公开(公告)号：US20120124335A1

公开(公告)日：2012-05-17

申请号：US13344339

申请日：2012-01-05

申请人： Gerald G. Pechanek ,  David Carl Strube ,  Edwin Franklin Barry ,  Charles W. Kurak, JR. ,  Carl Donald Busboom ,  Dale Edward Schneider ,  Nikos P. Pitsianis ,  Grayson Morris ,  Edward A. Wolff ,  Patrick R. Marchand ,  Ricardo E. Rodriguez ,  Marco C. Jacobs

发明人： Gerald G. Pechanek ,  David Carl Strube ,  Edwin Franklin Barry ,  Charles W. Kurak, JR. ,  Carl Donald Busboom ,  Dale Edward Schneider ,  Nikos P. Pitsianis ,  Grayson Morris ,  Edward A. Wolff ,  Patrick R. Marchand ,  Ricardo E. Rodriguez ,  Marco C. Jacobs

IPC分类号： G06F9/312

CPC分类号： G06F15/82 ,  G06F9/30145 ,  G06F11/263 ,  Y10S707/99943

摘要： Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.

摘要翻译： 这里描述了使用歧管阵列（ManArray）架构和指令语法的高成本有效和高效的实现的细节。 该方法的各个方面包括语法的规律性，指示集可以以数据库形式表示的相对容易程度，可以创建工具的就绪能力，即时生成自检代码和参数化测试用例。 可以很容易地映射参数化，并显着简化系统维护。

公开(公告)号：US20140059324A1

公开(公告)日：2014-02-27

申请号：US13771390

申请日：2013-02-20

申请人： Gerald George Pechanek ,  David Strube ,  Edwin Franklin Barry ,  Charles W. Kurak, JR. ,  Carl Donald Busboom ,  Dale Edward Schneider ,  Nikos P. Pitsianis ,  Grayson Morris ,  Edward A. Wolff ,  Patrick R. Marchand ,  Ricardo Rodriguez ,  Marco Jacobs

发明人： Gerald George Pechanek ,  David Strube ,  Edwin Franklin Barry ,  Charles W. Kurak, JR. ,  Carl Donald Busboom ,  Dale Edward Schneider ,  Nikos P. Pitsianis ,  Grayson Morris ,  Edward A. Wolff ,  Patrick R. Marchand ,  Ricardo Rodriguez ,  Marco Jacobs

IPC分类号： G06F15/82

CPC分类号： G06F15/82 ,  G06F9/30145 ,  G06F11/263 ,  Y10S707/99943

摘要： Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.

摘要翻译： 这里描述了使用歧管阵列（ManArray）架构和指令语法的高成本有效和高效的实现的细节。 该方法的各个方面包括语法的规律性，指示集可以以数据库形式表示的相对容易程度，可以创建工具的就绪能力，即时生成自检代码和参数化测试用例。 可以很容易地映射参数化，并显着简化系统维护。

公开(公告)号：US07257696B2

公开(公告)日：2007-08-14

申请号：US10641441

申请日：2003-08-15

申请人： Gerald George Pechanek ,  David Strube ,  Edward A. Wolff ,  Edwin Franklin Barry ,  Grayson Morris ,  Carl Donald Busboom ,  Dale Edward Schneider

发明人： Gerald George Pechanek ,  David Strube ,  Edward A. Wolff ,  Edwin Franklin Barry ,  Grayson Morris ,  Carl Donald Busboom ,  Dale Edward Schneider

IPC分类号： G06F9/302

CPC分类号： G06F9/3885 ,  G06F9/30014 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30149 ,  G06F9/325 ,  G06F9/3836 ,  G06F9/3853 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3887

摘要： Techniques for adding more complex instructions and their attendant multi-cycle execution units with a single instruction multiple data stream (SIMD) very long instruction word (VLIW) processing framework are described. In one aspect, an initiation mechanism also acts as a resynchronization mechanism to read the results of multi-cycle execution. This multi-purpose mechanism operates with a short instruction word (SIW) issue of the multi-cycle instruction, in a sequence processor (SP) alone, with a VLIW, and across all processing elements (PEs) individually or as an array of PEs. A number of advantageous floating point instructions are also described.

摘要翻译： 描述了使用单指令多数据流（SIMD）非常长的指令字（VLIW）处理框架来添加更复杂指令的技术及其伴随的多周期执行单元。 在一个方面，启动机制还充当重新同步机制以读取多周期执行的结果。 该多用途机构以单循环指令的短指令字（SIW）问题，单独的序列处理器（SP），VLIW以及跨所有处理元件（PE）单独地或作为PE阵列来操作 。 还描述了许多有利的浮点指令。

公开(公告)号：US07506137B2

公开(公告)日：2009-03-17

申请号：US11778303

申请日：2007-07-16

申请人： Gerald George Pechanek ,  David Strube ,  Edward A. Wolff ,  Edwin Franklin Barry ,  Grayson Morris ,  Carl Donald Busboom ,  Dale Edward Schneider

发明人： Gerald George Pechanek ,  David Strube ,  Edward A. Wolff ,  Edwin Franklin Barry ,  Grayson Morris ,  Carl Donald Busboom ,  Dale Edward Schneider

IPC分类号： G06F9/302

CPC分类号： G06F9/3885 ,  G06F9/30014 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30149 ,  G06F9/325 ,  G06F9/3836 ,  G06F9/3853 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3887

摘要： Techniques for adding more complex instructions and their attendant multi-cycle execution units with a single instruction multiple data stream (SIMD) very long instruction word (VLIW) processing framework are described. In one aspect, an initiation mechanism also acts as a resynchronization mechanism to read the results of multi-cycle execution. This multi-purpose mechanism operates with a short instruction word (SIW) issue of the multi-cycle instruction, in a sequence processor (SP) alone, with a VLIW, and across all processing elements (PEs) individually or as an array of PEs. A number of advantageous floating point instructions are also described.

摘要翻译： 描述了使用单指令多数据流（SIMD）非常长的指令字（VLIW）处理框架来添加更复杂指令的技术及其伴随的多周期执行单元。 在一个方面，启动机制还充当重新同步机制以读取多周期执行的结果。 该多用途机构以单循环指令的短指令字（SIW）问题，单独的序列处理器（SP），VLIW以及跨所有处理元件（PE）单独地或作为PE阵列来操作 。 还描述了许多有利的浮点指令。

公开(公告)号：US07058790B2

公开(公告)日：2006-06-06

申请号：US10786604

申请日：2004-02-25

申请人： Edwin Franklin Barry ,  Patrick R. Marchand ,  Gerald George Pechanek ,  Charles W. Kurak, Jr.

发明人： Edwin Franklin Barry ,  Patrick R. Marchand ,  Gerald George Pechanek ,  Charles W. Kurak, Jr.

IPC分类号： G06F11/30

CPC分类号： G06F9/30054 ,  G06F9/30101 ,  G06F9/30112 ,  G06F9/325

摘要： An eventpoint chaining apparatus for generalized event detection and action specification in a processing environment is described. In one aspect, the eventpoint chaining apparatus includes a first processor which has a programmable eventpoint module with an input trigger (InTrig) input. The first processing element detects an occurrence of a first processor event (p-event) and produces an OutTrigger (OT) signal. The eventpoint chaining apparatus also includes a second processor which has a programmable eventpoint module with an input trigger (InTrig) input which receives the OT signal from the first processing element. The second processing element detects an occurrence of a second p-event and produces, in response to the OT signal received from the first processing element and the detection of a second p-event, an eventpoint (EP) interrupt signal. The eventpoint chaining apparatus also includes a sequence processor interrupt control unit for receiving the EP interrupt signals indicating the occurrence of both the first and second p-events and causing a p-action in response to the occurrence of both the first and second p-events.

摘要翻译： 描述用于处理环境中的广义事件检测和动作规范的事件点链接装置。 一方面，事件点链接装置包括具有可输入触发（InTrig）输入的可编程事件点模块的第一处理器。 第一处理元件检测出第一处理器事件（p事件）的发生并产生OutTrigger（OT）信号。 事件点链接装置还包括具有可编程事件点模块的第二处理器，该可编程事件点模块具有从第一处理元件接收OT信号的输入触发（InTrig）输入。 第二处理元件检测第二p事件的发生，并且响应于从第一处理元件接收的OT信号和第二p事件的检测，产生事件点（EP）中断信号。 事件点链接装置还包括序列处理器中断控制单元，用于接收表示第一和第二p事件的发生的EP中断信号，并且响应于第一和第二p事件的发生而引起p动作 。

公开(公告)号：US07146487B2

公开(公告)日：2006-12-05

申请号：US10718415

申请日：2003-11-20

申请人： Thomas L. Drabenstott ,  Gerald George Pechanek ,  Edwin Franklin Barry ,  Charles W. Kurak, Jr.

发明人： Thomas L. Drabenstott ,  Gerald George Pechanek ,  Edwin Franklin Barry ,  Charles W. Kurak, Jr.

IPC分类号： G06F15/80

CPC分类号： G06F9/30094 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/30181 ,  G06F9/3842 ,  G06F9/3885 ,  G06F9/3887 ,  G06F9/3891 ,  G06F15/8007

摘要： General purpose flags (ACFs) are defined and encoded utilizing a hierarchical one-, two- or three-bit encoding. Each added bit provides a superset of the previous functionality. With condition combination, a sequential series of conditional branches based on complex conditions may be avoided and complex conditions can then be used for conditional execution. ACF generation and use can be specified by the programmer. By varying the number of flags affected, conditional operation parallelism can be widely varied, for example, from mono-processing to octal-processing in VLIW execution, and across an array of processing elements (PE)s. Multiple PEs can generate condition information at the same time with the programmer being able to specify a conditional execution in one processor based upon a condition generated in a different processor using the communications interface between the processing elements to transfer the conditions. Each processor in a multiple processor array may independently have different units conditionally operate based upon their ACFs.

公开(公告)号：US20130283012A1

公开(公告)日：2013-10-24

申请号：US13916877

申请日：2013-06-13

申请人： Edwin Franklin Barry ,  Patrick R. Marchand ,  Gerald George Pechanek ,  Larry D. Larsen

发明人： Edwin Franklin Barry ,  Patrick R. Marchand ,  Gerald George Pechanek ,  Larry D. Larsen

IPC分类号： G06F9/30

CPC分类号： G06F9/3865 ,  G06F9/30058 ,  G06F9/3861 ,  G06F9/4812 ,  G06F11/27 ,  G06F13/26 ,  Y02D10/14 ,  Y02D10/24

摘要： Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism.

摘要翻译： 描述了可扩展流水线阵列处理器环境中的中断检测和响应的硬件和软件技术。 利用这些技术，可以在包含多个处理元件和分布式存储器和寄存器文件的高度并行的可扩展流水线阵列处理中维持具有中断的顺序程序执行模型。 当发生中断时，接口信号提供给所有PE，以支持每个PE中的独立中断操作，取决于中断前的本地PE指令序列。 支持处理/元件异常中断，并为需要实时信号处理的嵌入式系统提供低延迟中断处理。 此外，使用分层中断结构，允许使用初次中断的通用调试方法和动态登场监视机制。