公开(公告)号：US6071314A

公开(公告)日：2000-06-06

申请号：US940154

申请日：1997-09-29

申请人： Glenn A. Baxter ,  Kiran B. Buch ,  Edwin S. Law

发明人： Glenn A. Baxter ,  Kiran B. Buch ,  Edwin S. Law

IPC分类号： G01R31/3185 ,  G06F11/27 ,  G01R31/3187 ,  G06F17/50

CPC分类号： G01R31/318583

摘要： A mask programmable IC is provided that includes dedicated boundary scan logic in the I/O cells. Valuable core logic resources therefore need not be consumed to implement boundary scan logic. In one embodiment, one boundary scan cell is provided per I/O cell. Another embodiment provides great flexibility in emulating any of several FPGAs in any of several packages. In this embodiment, two boundary scan cells are provided for each I/O pad, each cell alone being capable of providing the boundary scan functions associated with one I/O pad. By selectively choosing which of the boundary scan cells are included in the boundary scan data chain, the order of the boundary scan chain of the emulated FPGA in any of two or more packages can be reproduced. Boundary scan behavior is therefore emulated as well as the programmable logic behavior of the FPGA. In one embodiment, additional programmable interconnect lines traversing each boundary scan cell are provided. Theses interconnect lines can be used to programmably connect the data output of a first cell to the data input of second cell which need not be adjacent to the first.

摘要翻译： 提供了一种掩模可编程IC，其包括I / O单元中的专用边界扫描逻辑。 因此，不需要消耗有价值的核心逻辑资源来实现边界扫描逻辑。 在一个实施例中，每个I / O单元提供一个边界扫描单元。 另一个实施例提供了极大的灵活性来模拟几个封装中的任何一个中的几个FPGA中的任何一个。 在该实施例中，为每个I / O焊盘提供两个边界扫描单元，每个单元仅能够提供与一个I / O焊盘相关联的边界扫描功能。 通过选择性地选择边界扫描单元中的哪一个被包括在边界扫描数据链中，可以再现两个或更多个包中的任一个中的仿真FPGA的边界扫描链的顺序。 因此，边界扫描行为以及FPGA的可编程逻辑行为。 在一个实施例中，提供穿过每个边界扫描单元的附加可编程互连线。 这些互连线可以用于将第一单元的数据输出可编程地连接到不需要与第一单元相邻的第二单元的数据输入。

公开(公告)号：US06353921B1

公开(公告)日：2002-03-05

申请号：US09560438

申请日：2000-04-28

申请人： Edwin S. Law ,  Kiran B. Buch ,  Glenn A. Baxter ,  Raymond C. Pang

发明人： Edwin S. Law ,  Kiran B. Buch ,  Glenn A. Baxter ,  Raymond C. Pang

IPC分类号： G06F1750

CPC分类号： G06F17/5045

摘要： A hybrid HardWire device is provided that comprises a gate array core and a set of mask programmable I/O cells having I/O characteristics similar to those of an FPGA, i.e., sufficiently the same so the HardWire device can be used as a drop-in replacement for the FPGA with no redesign of the original system. Using this HardWire device, a user's design originally implemented in an FPGA can be emulated in the HardWire device, which then replaces the FPGA in the same board at a lower cost. In another embodiment, the I/O cells are mask programmable such that they can emulate the I/O characteristics of FPGAs from any of two or more FPGA families. This ability reduces the number of separate HardWire devices that must be designed, manufactured, tested, stored, and sold, and also simplifies the software required to convert designs to the new device. Some embodiments of the invention can also emulate other programmable devices such as PLDs.

摘要翻译： 提供了一种混合HardWire器件，其包括门阵列核心和一组具有类似于FPGA的I / O特性的掩码可编程I / O单元，即足够相同，因此HardWire器件可以用作下拉电阻， 替代FPGA而不重新设计原始系统。 使用这种HardWire设备，最初在FPGA中实现的用户设计可以在HardWire设备中进行仿真，然后以较低的成本替换同一块电路板中的FPGA。 在另一个实施例中，I / O单元是掩模可编程的，使得它们可以从两个或多个FPGA系列中的任何一个模拟FPGA的I / O特性。 这种能力减少了必须设计，制造，测试，存储和销售的单独的HardWire设备的数量，还简化了将设计转换为新设备所需的软件。 本发明的一些实施例还可以模拟其他可编程设备，例如PLD。

公开(公告)号：US6134517A

公开(公告)日：2000-10-17

申请号：US384714

申请日：1999-08-26

申请人： Glenn A. Baxter ,  Kiran B. Buch ,  Raymond C. Pang ,  Edwin S. Law

发明人： Glenn A. Baxter ,  Kiran B. Buch ,  Raymond C. Pang ,  Edwin S. Law

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318519

摘要： A method of implementing a boundary scan chain is provided using a programmable IC that includes dedicated boundary scan logic having a programmable boundary scan bit-order. Boundary scan cells are provided, each cell being capable of providing the boundary scan functions associated with one I/O pad. In a mask programmable device, dedicated tracks are provided for adding mask programmable interconnect lines. In other programmable ICs such as FPGAs or PLDs, programmable interconnect lines are provided. In either case, the interconnect lines are used to implement the boundary scan data chain. Using these lines, the programmed device can "swap the order" of I/O cells in the boundary scan data chain, or leave cells out of the chain entirely. In one embodiment, the interconnect lines traverse each cell, programmably connecting the data inputs and outputs of adjacent or non-adjacent boundary scan cells. In other embodiments, the interconnect lines are physically located outside the boundary scan cells, either in a ring between the cell and the core or in the core itself.

摘要翻译： 使用包括具有可编程边界扫描位顺序的专用边界扫描逻辑的可编程IC来提供实现边界扫描链的方法。 提供了边界扫描单元，每个单元能够提供与一个I / O垫相关联的边界扫描功能。 在掩模可编程设备中，提供专用轨道用于添加掩模可编程互连线。 在其他可编程IC（例如FPGA或PLD）中，提供可编程互连线。 在任一情况下，互连线用于实现边界扫描数据链。 使用这些线路，编程设备可以在边界扫描数据链中“交换I / O单元”的顺序，或将单元格完全从链中留出。 在一个实施例中，互连线穿过每个单元，可编程地连接相邻或非相邻边界扫描单元的数据输入和输出。 在其他实施例中，互连线物理地位于边界扫描单元外部，无论是在单元和芯之间的环中还是在芯本身中。

公开(公告)号：US6120551A

公开(公告)日：2000-09-19

申请号：US937809

申请日：1997-09-29

申请人： Edwin S. Law ,  Kiran B. Buch ,  Glenn A. Baxter ,  Raymond C. Pang

发明人： Edwin S. Law ,  Kiran B. Buch ,  Glenn A. Baxter ,  Raymond C. Pang

IPC分类号： G06F17/50 ,  G06F17/00

CPC分类号： G06F17/5045

摘要： A hybrid HardWire device is provided that comprises a gate array core and a set of mask programmable I/O cells having I/O characteristics similar to those of an FPGA, i.e., sufficiently the same so the HardWire device can be used as a drop-in replacement for the FPGA with no redesign of the original system. Using this HardWire device, a user's design originally implemented in an FPGA can be emulated in the HardWire device, which then replaces the FPGA in the same board at a lower cost. In another embodiment, the I/O cells are mask programmable such that they can emulate the I/O characteristics of FPGAs from any of two or more FPGA families. This ability reduces the number of separate HardWire devices that must be designed, manufactured, tested, stored, and sold, and also simplifies the software required to convert designs to the new device. Some embodiments of the invention can also emulate other programmable devices such as PLDs.

摘要翻译： 提供了一种混合HardWire器件，其包括门阵列核心和一组具有类似于FPGA的I / O特性的掩码可编程I / O单元，即足够相同，因此HardWire器件可以用作下拉电阻， 替代FPGA而不重新设计原始系统。 使用这种HardWire设备，最初在FPGA中实现的用户设计可以在HardWire设备中进行仿真，然后以较低的成本替换同一块电路板中的FPGA。 在另一个实施例中，I / O单元是掩模可编程的，使得它们可以从两个或多个FPGA系列中的任何一个模拟FPGA的I / O特性。 这种能力减少了必须设计，制造，测试，存储和销售的单独的HardWire设备的数量，还简化了将设计转换为新设备所需的软件。 本发明的一些实施例还可以模拟其他可编程设备，例如PLD。

公开(公告)号：US5991908A

公开(公告)日：1999-11-23

申请号：US939757

申请日：1997-09-29

申请人： Glenn A. Baxter ,  Kiran B. Buch ,  Raymond C. Pang ,  Edwin S. Law

发明人： Glenn A. Baxter ,  Kiran B. Buch ,  Raymond C. Pang ,  Edwin S. Law

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318519

摘要： A programmable IC is provided that includes dedicated boundary scan logic having a programmable boundary scan bit-order. Boundary scan cells are provided, each cell being capable of providing the boundary scan functions associated with one I/O pad. In a mask programmable device, dedicated tracks are provided for adding mask programmable interconnect lines. In other programmable ICs such as FPGAs or PLDs, programmable interconnect lines are provided. In either case, the interconnect lines are used to implement the boundary scan data chain. Using these lines, the programmed device can "swap the order" of I/O cells in the boundary scan data chain, or leave cells out of the chain entirely. In one embodiment, the interconnect lines traverse each cell, programmably connecting the data inputs and outputs of adjacent or non-adjacent boundary scan cells. In other embodiments, the interconnect lines are physically located outside the boundary scan cells, either in a ring between the cell and the core or in the core itself.

摘要翻译： 提供了一种可编程IC，其包括具有可编程边界扫描比特顺序的专用边界扫描逻辑。 提供了边界扫描单元，每个单元能够提供与一个I / O垫相关联的边界扫描功能。 在掩模可编程设备中，提供专用轨道用于添加掩模可编程互连线。 在其他可编程IC（例如FPGA或PLD）中，提供可编程互连线。 在任一情况下，互连线用于实现边界扫描数据链。 使用这些线路，编程设备可以在边界扫描数据链中“交换I / O单元”的顺序，或将单元格完全从链中留出。 在一个实施例中，互连线穿过每个单元，可编程地连接相邻或非相邻边界扫描单元的数据输入和输出。 在其他实施例中，互连线物理地位于边界扫描单元外部，无论是在单元和芯之间的环中还是在芯本身中。

公开(公告)号：US06226779B1

公开(公告)日：2001-05-01

申请号：US09546461

申请日：2000-04-10

申请人： Glenn A. Baxter ,  Kiran B. Buch ,  Edwin S. Law

发明人： Glenn A. Baxter ,  Kiran B. Buch ,  Edwin S. Law

IPC分类号： G06F1127

CPC分类号： G01R31/318583

摘要： A mask programmable IC is provided that includes dedicated boundary scan logic in the I/O cells. Valuable core logic resources therefore need not be consumed to implement boundary scan logic. In one embodiment, one boundary scan cell is provided per I/O cell. Another embodiment provides great flexibility in emulating any of several FPGAs in any of several packages. In this embodiment, two boundary scan cells are provided for each I/O pad, each cell alone being capable of providing the boundary scan functions associated with one I/O pad. By selectively choosing which of the boundary scan cells are included in the boundary scan data chain, the order of the boundary scan chain of the emulated FPGA in any of two or more packages can be reproduced. Boundary scan behavior is therefore emulated as well as the programmable logic behavior of the FPGA. In one embodiment, additional programmable interconnect lines traversing each boundary scan cell are provided. These interconnect lines can be used to programmably connect the data output of a first cell to the data input of second cell which need not be adjacent to the first.

摘要翻译： 提供了一种掩模可编程IC，其包括I / O单元中的专用边界扫描逻辑。 因此，不需要消耗有价值的核心逻辑资源来实现边界扫描逻辑。 在一个实施例中，每个I / O单元提供一个边界扫描单元。 另一个实施例提供了极大的灵活性来模拟几个封装中的任何一个中的几个FPGA中的任何一个。 在该实施例中，为每个I / O焊盘提供两个边界扫描单元，每个单元仅能够提供与一个I / O焊盘相关联的边界扫描功能。 通过选择性地选择边界扫描单元中的哪一个被包括在边界扫描数据链中，可以再现两个或更多个包中的任一个中的仿真FPGA的边界扫描链的顺序。 因此，边界扫描行为以及FPGA的可编程逻辑行为。 在一个实施例中，提供穿过每个边界扫描单元的附加可编程互连线。 这些互连线可用于将第一单元的数据输出可编程地连接到不需要与第一单元相邻的第二单元的数据输入。

公开(公告)号：US08134875B2

公开(公告)日：2012-03-13

申请号：US12329993

申请日：2008-12-08

申请人： Glenn A. Baxter

发明人： Glenn A. Baxter

IPC分类号： G11C7/00 ,  G06F12/06 ,  G06F13/00

CPC分类号： G11C5/02 ,  G11C5/04

摘要： A data storage system includes a first circuit board, a plurality of sockets coupled to the first circuit board, an connector coupled to each of the sockets for coupling each of the sockets to external circuitry, and a plurality of memory modules, each memory module disposed within one of the sockets. The memory module includes a circuit board, an integrated circuit device having configurable blocks, DRAM devices that form parallel channels of DRAM memory and flash memory devices that form parallel channels of flash memory. The memory module also includes an interface electrically coupled to the integrated circuit device for coupling input and output between the integrated circuit device and external circuitry.

摘要翻译： 数据存储系统包括第一电路板，耦合到第一电路板的多个插座，连接到每个插座的连接器，用于将每个插座连接到外部电路，以及多个存储器模块，每个存储器模块设置 在一个插座内。 存储器模块包括电路板，具有可配置块的集成电路器件，形成DRAM存储器的并行通道的DRAM器件以及形成闪速存储器的并行通道的闪存器件。 存储器模块还包括电耦合到集成电路器件的接口，用于在集成电路器件和外部电路之间耦合输入和输出。

公开(公告)号：US07720636B1

公开(公告)日：2010-05-18

申请号：US11707015

申请日：2007-02-14

申请人： Glenn A. Baxter ,  Jennifer R. Lilley

发明人： Glenn A. Baxter ,  Jennifer R. Lilley

IPC分类号： G21C17/00

CPC分类号： G06F13/1694 ,  G06F11/3409 ,  G06F11/349 ,  G06F2201/86 ,  G06F2201/87 ,  G06F2201/88

摘要： Performance monitors (PMs) are provided in a system to identify the execution time for data being transferred within the system and determine operation parameters of the system based on the rate data is transferred. The operation parameters are then used to configure hardware within the system. The PMs can provide a histogram of the transactions usable to evaluate system performance. The PMs can provide a time line diagram of the transactions to show the specific order the transactions occurred. The PMs can be provided in a multi-port memory controller (MPMC) to monitor the speed of read and write transactions from the MPMC ports, and used to configure logic within the MPMC to maximize the rate of data flow.

摘要翻译： 在系统中提供性能监视器（PM）以识别在系统内正在传送的数据的执行时间，并基于传送速率数据确定系统的操作参数。 然后，操作参数用于配置系统内的硬件。 PM可以提供可用于评估系统性能的事务的直方图。 PM可以提供交易的时间线图，以显示交易发生的具体顺序。 PM可以在多端口存储器控制器（MPMC）中提供，以监控来自MPMC端口的读写事务的速度，并用于配置MPMC内的逻辑以最大化数据流量。

公开(公告)号：US07225278B1

公开(公告)日：2007-05-29

申请号：US10824713

申请日：2004-04-15

申请人： Glenn A. Baxter ,  Christopher J. Borrelli

发明人： Glenn A. Baxter ,  Christopher J. Borrelli

IPC分类号： G06F13/28 ,  G06F13/00

CPC分类号： G06F13/34 ,  G06F13/28

摘要： Method and apparatus for controlling direct access to memory circuitry by a device is described. In one example, a streaming interface is configured to transmit and receive a communication sequence to and from the device. Control logic is configured to implement a plurality of direct memory access (DMA) engines. The DMA engines are configured to read and write data to and from the memory circuitry. A set of registers is configured to store control data for the plurality of DMA engines.

摘要翻译： 描述了用于控制由设备直接访问存储器电路的方法和装置。 在一个示例中，流接口被配置为向设备发送和从设备接收通信序列。 控制逻辑被配置为实现多个直接存储器访问（DMA）引擎。 DMA引擎被配置为从存储器电路读取和写入数据。 一组寄存器被配置为存储多个DMA引擎的控制数据。

公开(公告)号：US06675309B1

公开(公告)日：2004-01-06

申请号：US09615365

申请日：2000-07-13

申请人： Glenn A. Baxter

发明人： Glenn A. Baxter

IPC分类号： G06F104

CPC分类号： G06F17/5045

摘要： Method and circuits to create reduced field programmable gate arrays (RFPGA) from the configuration data of field programmable gate arrays (FPGA) are disclosed. The configurable elements of the FPGA are replaced with standard cell circuits that reproduce the functionality of the configured FPGA. Specifically, reduced logic blocks are derived from the configuration data of configurable logic blocks. The reduced logic blocks are arranged in a similar layout to the original CLBs so that timing relationships remain similar in the RFPGA and FPGA. The actual timing of the RFPGA can be modified by increasing or decreasing the timing delay on various signal paths based on the FPGA design or additional timing constraints. To reduce the time required to generate RFPGAs, a database can be used to contain configurable logic block models and the corresponding reduced logic block models.

摘要翻译： 公开了从现场可编程门阵列（FPGA）的配置数据创建简化的现场可编程门阵列（RFPGA）的方法和电路。 FPGA的可配置元件被重现了配置的FPGA功能的标准单元电路所取代。 具体来说，从可配置逻辑块的配置数据导出缩减的逻辑块。 减少的逻辑块以与原始CLB相似的布局布置，使得RFPGA和FPGA中的时序关系保持相似。 RFPGA的实际定时可以通过根据FPGA设计或额外的时序约束增加或减少各种信号路径上的定时延迟来进行修改。 为了减少生成RFPGA所需的时间，可以使用数据库来包含可配置的逻辑块模型和相应的减少的逻辑块模型。