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    HIGH PERFORMANCE CACHE DIRECTORY ERROR CORRECTION CODE
    1.
    发明申请
    HIGH PERFORMANCE CACHE DIRECTORY ERROR CORRECTION CODE 失效
    高性能缓存目录错误修正代码

    公开(公告)号：US20110320919A1

    公开(公告)日：2011-12-29

    申请号：US12822889

    申请日：2010-06-24

    申请人： Ekaterina M. Ambroladze ,  Patrick J. Meaney ,  Arthur J. O'Neill, JR.

    发明人： Ekaterina M. Ambroladze ,  Patrick J. Meaney ,  Arthur J. O'Neill, JR.

    IPC分类号： H03M13/15 ,  G06F11/10

    CPC分类号： G06F11/1064 ,  H03M13/19

    摘要： Defining a set of correctable error and uncorrectable error syndrome code points, generating an error correction code (ECC) syndrome decode, regarding the uncorrectable error syndrome code points as “don't cares” and logically minimizing the ECC syndrome decode for the determination of the correctable error syndrome code points based on the regarding of the uncorrectable error syndrome code points as the “don't cares” whereby output data can be ignored for the uncorrectable error syndrome code points.

    摘要翻译： 定义一组可纠正的错误和不可校正的错误校正码代码点，产生纠错码（ECC）校正码解码，关于不可校正的错误校正码码点为“不关心”，并在逻辑上最小化ECC校验码解码以确定 基于关于不可校正误差校验码码点的可校正误差校验码码点作为“不关心”，由此对于不可校正的误码校验码码点可以忽略输出数据。

    USER-CONTROLLED TARGETED CACHE PURGE
    2.
    发明申请
    USER-CONTROLLED TARGETED CACHE PURGE 失效
    用户控制的高速缓存池

    公开(公告)号：US20110320732A1

    公开(公告)日：2011-12-29

    申请号：US12822428

    申请日：2010-06-24

    申请人： Ekaterina M. Ambroladze ,  Patrick J. Meaney ,  Arthur J. O'Neill, JR.

    发明人： Ekaterina M. Ambroladze ,  Patrick J. Meaney ,  Arthur J. O'Neill, JR.

    IPC分类号： G06F12/08

    CPC分类号： G06F12/126

    摘要： User-controlled targeted cache purging includes receiving a request to perform an operation to purge data from a cache, the request including an index identifier identifying an index associated with the cache. The index specifies a portion of the cache to be purged. The user-controlled targeted cache purging also includes purging the data from the cache, and providing notification of successful completion of the operation.

    摘要翻译： 用户控制的目标缓存清除包括接收执行从缓存清除数据的操作的请求，所述请求包括标识与高速缓存相关联的索引的索引标识符。 该索引指定要清除的缓存的一部分。 用户控制的目标缓存清除还包括从缓存中清除数据，并提供成功完成操作的通知。

    High performance cache directory error correction code
    3.
    发明授权
    High performance cache directory error correction code 失效
    高性能缓存目录纠错码

    公开(公告)号：US08365055B2

    公开(公告)日：2013-01-29

    申请号：US12822889

    申请日：2010-06-24

    申请人： Ekaterina M. Ambroladze ,  Patrick J. Meaney ,  Arthur J. O'Neill, Jr.

    发明人： Ekaterina M. Ambroladze ,  Patrick J. Meaney ,  Arthur J. O'Neill, Jr.

    IPC分类号： H03M13/00 ,  G11C29/00

    CPC分类号： G06F11/1064 ,  H03M13/19

    摘要： Defining a set of correctable error and uncorrectable error syndrome code points, generating an error correction code (ECC) syndrome decode, regarding the uncorrectable error syndrome code points as “don't cares” and logically minimizing the ECC syndrome decode for the determination of the correctable error syndrome code points based on the regarding of the uncorrectable error syndrome code points as the “don't cares” whereby output data can be ignored for the uncorrectable error syndrome code points.

    摘要翻译： 定义一组可纠正的错误和不可纠正的错误校正码代码点，生成关于不可校正错误校验码码点的纠错码（ECC）校验码解码，因为不考虑和逻辑地最小化用于确定可纠正错误的ECC校验码解码 基于关于不可校正误差校正码码点的校验码码点，因为不需要关心的输出数据可以被忽略用于不可校正的误码校验码码点。

    User-controlled targeted cache purge
    4.
    发明授权
    User-controlled targeted cache purge 失效
    用户控制的目标缓存清除

    公开(公告)号：US08364899B2

    公开(公告)日：2013-01-29

    申请号：US12822428

    申请日：2010-06-24

    申请人： Ekaterina M. Ambroladze ,  Patrick J. Meaney ,  Arthur J. O'Neill, Jr.

    发明人： Ekaterina M. Ambroladze ,  Patrick J. Meaney ,  Arthur J. O'Neill, Jr.

    IPC分类号： G06F12/12 ,  G06F13/00

    CPC分类号： G06F12/126

    摘要： User-controlled targeted cache purging includes receiving a request to perform an operation to purge data from a cache, the request including an index identifier identifying an index associated with the cache. The index specifies a portion of the cache to be purged. The user-controlled targeted cache purging also includes purging the data from the cache, and providing notification of successful completion of the operation.

    摘要翻译： 用户控制的目标缓存清除包括接收执行从缓存清除数据的操作的请求，所述请求包括标识与高速缓存相关联的索引的索引标识符。 该索引指定要清除的缓存的一部分。 用户控制的目标缓存清除还包括从缓存中清除数据，并提供成功完成操作的通知。

    Cache coherency protocol with built in avoidance for conflicting responses
    5.
    发明授权
    Cache coherency protocol with built in avoidance for conflicting responses 失效
    缓存一致性协议内置避免冲突的响应

    公开(公告)号：US08250308B2

    公开(公告)日：2012-08-21

    申请号：US12031977

    申请日：2008-02-15

    申请人： Vesselina K. Papazova ,  Ekaterina M. Ambroladze ,  Michael A. Blake ,  Pak-kin Mak ,  Arthur J. O'Neill, Jr. ,  Craig R. Waters

    发明人： Vesselina K. Papazova ,  Ekaterina M. Ambroladze ,  Michael A. Blake ,  Pak-kin Mak ,  Arthur J. O'Neill, Jr. ,  Craig R. Waters

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0831

    摘要： The method includes initiating a processor request to a cache in a requesting node and broadcasting the processor request to remote nodes when the processor request encounters a local cache miss, performing a directory search of each remote cache to determine a state of a target line's address and an ownership state of a specified address, returning the state of the target line to the requesting node and forming a combined response, and broadcasting the combined response to each remote node. During a fetch operation, when the directory search indicates an IM or a Target Memory node on a remote node, data is sourced from the respective remote cache and forwarded to the requesting node while protecting the data, and during a store operation, the data is sourced from the requesting node and protected while being forwarded to the IM or the Target Memory node after coherency has been established.

    摘要翻译： 该方法包括：当处理器请求遇到本地高速缓存未命中时，向请求节点中的高速缓存发起处理器请求并将处理器请求广播到远程节点，执行每个远程高速缓存的目录搜索以确定目标行的地址的状态，以及 指定地址的所有权状态，将目标行的状态返回到请求节点并形成组合响应，并将组合的响应广播到每个远程节点。 在获取操作期间，当目录搜索指示远程节点上的IM或目标存储器节点时，数据来自相应的远程高速缓存并且在保护数据的同时被转发到请求节点，并且在存储操作期间，数据是 源自请求节点，并且在一致性被建立之后被转发到IM或目标存储器节点时被保护。

    DYNAMIC PIPELINE CACHE ERROR CORRECTION
    6.
    发明申请
    DYNAMIC PIPELINE CACHE ERROR CORRECTION 失效
    动态管道缓存错误校正

    公开(公告)号：US20110320866A1

    公开(公告)日：2011-12-29

    申请号：US12822437

    申请日：2010-06-24

    申请人： Ekaterina M. Ambroladze ,  Michael Fee ,  Edward T. Gerchman ,  Arthur J. O'Neill, JR.

    发明人： Ekaterina M. Ambroladze ,  Michael Fee ,  Edward T. Gerchman ,  Arthur J. O'Neill, JR.

    IPC分类号： G06F11/14

    CPC分类号： G06F11/1048

    摘要： Dynamic pipeline cache error correction includes receiving a request to perform an operation that requires a storage cache slot, the storage cache slot residing in a cache. The dynamic pipeline cache error correction also includes accessing the storage cache slot, determining a cache hit for the storage cache slot, identifying and correcting any correctable soft errors associated with the storage cache slot. The dynamic cache error correction further includes updating the cache with results of corrected data.

    摘要翻译： 动态流水线高速缓存错误校正包括接收执行需要存储高速缓存时隙的操作的请求，存储高速缓冲存储器时隙驻留在高速缓存中。 动态流水线高速缓存错误校正还包括访问存储高速缓存时隙，确定存储高速缓存时隙的高速缓存命中，识别和校正与存储高速缓存槽相关联的任何可校正的软错误。 动态高速缓存错误校正还包括用校正数据的结果更新高速缓存。

    Managing dataflow in a temporary memory
    7.
    发明授权
    Managing dataflow in a temporary memory 失效
    在临时内存中管理数据流

    公开(公告)号：US08392621B2

    公开(公告)日：2013-03-05

    申请号：US12820589

    申请日：2010-06-22

    申请人： Ekaterina M. Ambroladze ,  Deanna Postles Dunn Berger ,  Michael Fee ,  Arthur J. O'Neill, Jr. ,  Diana Lynn Orf ,  Robert J. Sonnelitter, III

    发明人： Ekaterina M. Ambroladze ,  Deanna Postles Dunn Berger ,  Michael Fee ,  Arthur J. O'Neill, Jr. ,  Diana Lynn Orf ,  Robert J. Sonnelitter, III

    IPC分类号： G06F3/00

    CPC分类号： G06F11/0751 ,  G06F11/0724 ,  G06F11/073 ,  G06F12/0897 ,  Y02D10/13

    摘要： A method of managing a temporary memory includes: receiving a request to transfer data from a source location to a destination location, the data transfer request associated with an operation to be performed, the operation selected from an input into an intermediate temporary memory and an output; checking a two-state indicator associated with the temporary memory, the two-state indicator having a first state indicating that an immediately preceding operation on the temporary memory was an input to the temporary memory and a second state indicating that the immediately preceding operation was an output from the temporary memory; and performing the operation responsive to one of: the operation being an input operation and the two-state indicator being in the second state, indicating that the immediately preceding operation was an output; and the operation being an output operation and the two-state indicator being in the first state, indicating that the immediately preceding operation was an input.

    摘要翻译： 管理临时存储器的方法包括：接收从源位置传送数据到目的地位置的请求，与要执行的操作相关联的数据传输请求，从输入中选择的中间临时存储器和输出 ; 检查与临时存储器相关联的两状态指示符，两状态指示符具有指示临时存储器上的紧接在前的操作是临时存储器的输入的第一状态，以及指示紧接在前的操作是第二状态的第二状态 从临时存储器输出; 并且响应于以下操作中的一个执行操作：作为输入操作的操作和处于第二状态的两状态指示器，指示紧接在前的操作是输出; 操作是输出操作，两状态指示灯处于第一状态，表示紧接在前的操作是输入。

    Error detection and recovery in a shared pipeline
    9.
    发明授权
    Error detection and recovery in a shared pipeline 失效
    共享管道中的错误检测和恢复

    公开(公告)号：US08522076B2

    公开(公告)日：2013-08-27

    申请号：US12821871

    申请日：2010-06-23

    申请人： Ekaterina M. Ambroladze ,  Deanna Postles Dunn Berger ,  Michael Fee ,  Arthur J. O'Neill, Jr. ,  Diana Lynn Orf ,  Robert J. Sonnelitter, III

    发明人： Ekaterina M. Ambroladze ,  Deanna Postles Dunn Berger ,  Michael Fee ,  Arthur J. O'Neill, Jr. ,  Diana Lynn Orf ,  Robert J. Sonnelitter, III

    IPC分类号： G06F11/00

    CPC分类号： G06F11/0751 ,  G06F11/0724 ,  G06F11/0793

    摘要： A pipelined processing device includes: a processor configured to receive a request to perform an operation; a plurality of processing controllers configured to receive at least one instruction associated with the operation, each of the plurality of processing controllers including a memory to store at least one instruction therein; a pipeline processor configured to receive and process the at least one instruction, the pipeline processor including shared error detection logic configured to detect a parity error in the at least one instruction as the at least one instruction is processed in a pipeline and generate an error signal; and a pipeline bus connected to each of the plurality of processing controllers and configured to communicate the error signal from the error detection logic.

    摘要翻译： 流水线处理装置包括：被配置为接收执行操作的请求的处理器; 多个处理控制器，被配置为接收与所述操作相关联的至少一个指令，所述多个处理控制器中的每个处理控制器包括用于在其中存储至少一个指令的存储器; 流水线处理器，被配置为接收和处理所述至少一个指令，所述流水线处理器包括被配置为在流水线中处理所述至少一个指令时检测所述至少一个指令中的奇偶校验错误的共享错误检测逻辑，并且生成错误信号 ; 以及连接到所述多个处理控制器中的每个处理控制器并被配置为传送来自所述错误检测逻辑的所述错误信号的流水线总线。