公开(公告)号：US20200169691A1

公开(公告)日：2020-05-28

申请号：US16695886

申请日：2019-11-26

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE ,  KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Se-Yoon JEONG ,  Min Hyuk KIM ,  Shinyoung YI ,  Jung-Won KANG ,  Hui-Yong KIM ,  Hakyeong KIM

IPC: H04N7/00 ,  H04N5/58

Abstract: Disclosed herein are a method and apparatus for luminance-adaptive opto-electrical transfer and luminance-adaptive electro-optical transfer. For video transmission and compression, opto-electrical transfer and electro-optical transfer are required. The surround luminance and luminance range of an image are taken into consideration when performing opto-electrical transfer and electro-optical transfer. An opto-electrical transfer function may be derived based on a contrast sensitivity function that takes into consideration the surround luminance of an image. Also, parameters relevant to surround luminance may be signaled from an encoding apparatus to a decoding apparatus, and an electro-optical transfer function may be derived based on the parameters.

公开(公告)号：US20170264313A1

公开(公告)日：2017-09-14

申请号：US15452906

申请日：2017-03-08

Applicant: Electronics and Telecommunications Research Institute

Inventor： In Ki LEE ,  Min Hyuk KIM

IPC: H03M13/11 ,  H03M13/00

CPC classification number: H03M13/1105 ,  H03M13/1111 ,  H03M13/1131 ,  H03M13/1165 ,  H03M13/118 ,  H03M13/6522

Abstract: Provided is a decoder that is at least temporarily implemented by a processor of a computing device. The decoder includes a calculator configured to repeatedly perform a calculation of a bit node and a calculation of a check node for an input frame, a processor configured to determine whether to input the bit node to a next calculation of the check node based on a code of the bit node, and an outputter configured to output a decoded code based on the bit node determined to be input.

公开(公告)号：US20140089766A1

公开(公告)日：2014-03-27

申请号：US14031279

申请日：2013-09-19

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： In Ki LEE ,  Deock Gil OH ,  Ji Won JUNG ,  Min Hyuk KIM

IPC: H03M13/13

CPC classification number: H03M13/13 ,  H03M13/1165 ,  H03M13/611 ,  H03M13/6561

Abstract: Provided is a low density parity check (LDPC) encoding apparatus and method that may store M registers each including N bits, obtain N×M parity bits by performing a partial parallel operation an N×M number of times with respect to the M registers, and mutually invert subsequent N parity bits periodically, based on previous parity bits for each Nth parity bit of the N×M parity bits, respectively.

Abstract translation: 提供了一种低密度奇偶校验（LDPC）编码装置和方法，其可以存储每个包括N比特的M个寄存器，通过相对于M个寄存器执行N×M次次的部分并行操作来获得N×M个奇偶校验位， 并且分别基于N×M个奇偶校验位的每第N个奇偶校验位的先前奇偶校验位周期性地相互反转后续的N个奇偶校验位。

公开(公告)号：US20180138924A1

公开(公告)日：2018-05-17

申请号：US15809392

申请日：2017-11-10

Applicant: Electronics and Telecommunications Research Institute

Inventor： Min Hyuk KIM ,  Youngmin CHOI

IPC: H03M13/11

Abstract: Provided is a method of scheduling a parity check matrix, the method performed by a low-density parity-check (LDPC) decoder, the method including checking at least one non-zero elemental variable node in the parity check matrix, identifying a first index of a row of the parity check matrix in the at least one non-zero elemental variable node, extracting a column in which the at least one non-zero elemental variable node is positionable from the parity check matrix using the first index, and mapping the at least one non-zero elemental variable node to the extracted column based on an arrangement, and identifying a second index of the column of the parity check matrix through the mapped at least one non-zero elemental variable node.

公开(公告)号：US20150237407A1

公开(公告)日：2015-08-20

申请号：US14617087

申请日：2015-02-09

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： In Ki LEE ,  Min Hyuk KIM ,  Deock Gil OH ,  Ji Won JUNG

IPC: H04N21/643 ,  H04L25/03 ,  H04L1/00 ,  H04N21/61 ,  H04N21/44

CPC classification number: H04L25/03 ,  H04L1/005 ,  H04L1/0057 ,  H04L1/0071 ,  H04L25/03318

Abstract: Disclosed are a signal receiving apparatus based on FTN and a signal decoding method thereof, and the apparatus includes: an equalizer calculating, when a signal sampled by Fast to Nyquist (FTN) is received on a communication channel, a posterior probability of information bits and calculating a log likelihood ratio by using the calculated posterior probability; a deinterleaver deinterleaving bit data output from the equalizer; a decoder correcting of signal interference of the data bits deinterleaved by the deinterleaver by using the LLR and decoding the corrected signal interference; and an interleaver interleaving data output from the decoder to provide the interleaved data to the equalizer.

Abstract translation: 公开了一种基于FTN的信号接收装置及其信号解码方法，该装置包括：均衡器，当在通信信道上接收到通过快速到奈奎斯特（FTN）采样的信号时，计算信息比特的后验概率， 通过使用计算的后验概率计算对数似然比; 解交织器对来自均衡器的比特数据进行解交织; 通过使用LLR对由解交织器解交错的数据位的信号干扰进行校正的解码器，对解调后的信号干扰进行解码; 交织器交织从解码器输出的数据，以将间隔的数据提供给均衡器。