公开(公告)号：US07638850B2

公开(公告)日：2009-12-29

申请号：US11440624

申请日：2006-05-24

申请人： Eli Lusky ,  Assaf Shappir ,  Rustom Irani ,  Boaz Eitan

发明人： Eli Lusky ,  Assaf Shappir ,  Rustom Irani ,  Boaz Eitan

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  H01L21/28282 ,  H01L21/32139 ,  H01L27/11568 ,  H01L29/66833

摘要： A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns.

摘要翻译： 一种用于创建非易失性存储器阵列的方法包括至少在给定宽度的掩模列之间以及至少穿过覆盖衬底的ONO层之间的衬底中注入口袋植入物，从掩模柱产生增加宽度的多晶硅柱，产生位 至少在增宽宽度的多晶硅柱之间并且至少在多晶硅柱之间沉积氧化物的衬底中的线。

公开(公告)号：US20060211188A1

公开(公告)日：2006-09-21

申请号：US11440624

申请日：2006-05-24

申请人： Eli Lusky ,  Assaf Shappir ,  Rustom Irani ,  Boaz Eitan

发明人： Eli Lusky ,  Assaf Shappir ,  Rustom Irani ,  Boaz Eitan

IPC分类号： H01L21/8238 ,  H01L21/3205 ,  H01L21/31

CPC分类号： H01L27/115 ,  H01L21/28282 ,  H01L21/32139 ,  H01L27/11568 ,  H01L29/66833

摘要： A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns.

公开(公告)号：US07964459B2

公开(公告)日：2011-06-21

申请号：US12654092

申请日：2009-12-10

申请人： Eli Lusky ,  Assaf Shappir ,  Rustom Irani ,  Boaz Eitan

发明人： Eli Lusky ,  Assaf Shappir ,  Rustom Irani ,  Boaz Eitan

IPC分类号： H01L21/8238

CPC分类号： H01L27/115 ,  H01L21/28282 ,  H01L21/32139 ,  H01L27/11568 ,  H01L29/66833

摘要： A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns.

摘要翻译： 一种用于创建非易失性存储器阵列的方法包括至少在给定宽度的掩模列之间以及至少穿过覆盖衬底的ONO层之间的衬底中注入口袋植入物，从掩模柱产生增加宽度的多晶硅柱，产生位 至少在增宽宽度的多晶硅柱之间并且至少在多晶硅柱之间沉积氧化物的衬底中的线。

公开(公告)号：US20100173464A1

公开(公告)日：2010-07-08

申请号：US12654092

申请日：2009-12-10

申请人： Eli Lusky ,  Assaf Shappir ,  Rustom Irani ,  Boaz Eitan

发明人： Eli Lusky ,  Assaf Shappir ,  Rustom Irani ,  Boaz Eitan

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L21/28282 ,  H01L21/32139 ,  H01L27/11568 ,  H01L29/66833

摘要： A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns.

摘要翻译： 一种用于创建非易失性存储器阵列的方法包括至少在给定宽度的掩模列之间以及至少穿过覆盖衬底的ONO层之间的衬底中注入口袋植入物，从掩模柱产生增加宽度的多晶硅柱，产生位 至少在增宽宽度的多晶硅柱之间并且至少在多晶硅柱之间沉积氧化物的衬底中的线。

公开(公告)号：US20080025084A1

公开(公告)日：2008-01-31

申请号：US11882787

申请日：2007-08-06

申请人： Rustom Irani ,  Boaz Eitan ,  Assaf Shappir

发明人： Rustom Irani ,  Boaz Eitan ,  Assaf Shappir

IPC分类号： G11C11/34 ,  H01L21/336 ,  H01L29/792

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： A non-volatile memory device includes a plurality of word line areas each separated from its neighbor by a contact area, an oxide-nitride-oxide (ONO) layer within the word line areas and at least partially within the contact areas and protective elements, generated when spacers are formed in the periphery area, to protect silicon under the ONO layer in the contact areas. A non-volatile memory device includes a plurality of word line areas each separated from its neighbor by a contact area and bitline oxides whose height:distance aspect ratio (T:D) is at least 25% greater than the maximum height:distance (Tg:Dg) ratio of gate electrodes in the CMOS periphery to ensure remnants of sidewall material between bitlines after sidewall spacer etch, thus protecting silicon in a subsequent word line salicidation step.

摘要翻译： 非易失性存储器件包括多个字线区域，每个字线区域与其相邻部分由接触区域分开，字线区域内的氧化物 - 氧化物 - 氧化物（ONO）层和至少部分地在接触区域内的保护元件， 当在周边区域中形成间隔物时产生，以保护接触区域内的ONO层下的硅。 非易失性存储器件包括多个字线区域，每个字线区域与其相邻的接触区域分开，并且其高度：距离长宽比（T：D）比最大高度大至少25％的位线氧化物：距离（Tg ：Dg）CMOS外围的栅电极的比例，以确保在侧壁间隔物蚀刻之后位线之间的侧壁材料的残留物，从而在随后的字线盐化步骤中保护硅。

公开(公告)号：US07638835B2

公开(公告)日：2009-12-29

申请号：US11646430

申请日：2006-12-28

申请人： Rustom Irani ,  Boaz Eitan ,  Ilan Bloom ,  Assaf Shappir

发明人： Rustom Irani ,  Boaz Eitan ,  Ilan Bloom ,  Assaf Shappir

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/11573

摘要： An NVM cell such as an NROM cell is formed using a portion of one ONO stack and an adjacent portion of a neighboring NROM stack. A gate structure is formed between (and atop) the two ONO portions, or “strips” (or “stripes”). This provides having two physically separated charge storage regions (nitride “strips”, or “stripes”) in each memory cell.

摘要翻译： 使用一个ONO堆栈的一部分和相邻NROM堆栈的相邻部分来形成诸如NROM单元的NVM单元。 在（和顶部）两个ONO部分或“条带”（或“条纹”）之间形成栅极结构。 这提供了在每个存储单元中具有两个物理分离的电荷存储区域（氮化物“条带”或“条纹”）。

公开(公告)号：US20070120180A1

公开(公告)日：2007-05-31

申请号：US11604029

申请日：2006-11-24

申请人： Boaz Eitan ,  Rustom Irani ,  Assaf Shappir

发明人： Boaz Eitan ,  Rustom Irani ,  Assaf Shappir

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/105 ,  Y10T29/49002

摘要： A non-volatile memory chip has word lines spaced a sub-F (sub-minimum feature size F) width apart with extensions of the word lines in at least two transition areas. Neighboring extensions are spaced at least F apart. The present invention also includes a method for word-line patterning of a non-volatile memory chip which includes generating sub-F word lines with extensions in transition areas for connecting to peripheral transistors from mask generated elements with widths of at least F.

摘要翻译： 非易失性存储器芯片具有与至少两个过渡区域中的字线的扩展分开的子F（子最小特征尺寸F）宽度的字线。 相邻的延伸部分间隔至少F。 本发明还包括一种用于非易失性存储器芯片的字线图案化的方法，该方法包括在具有至少为F的宽度的掩模生成元件中生成具有用于连接到外围晶体管的过渡区域中的扩展的子F字线。

公开(公告)号：US20080239807A1

公开(公告)日：2008-10-02

申请号：US12149202

申请日：2008-04-29

申请人： Boaz Eitan ,  Rustom Irani ,  Assaf Shappir

发明人： Boaz Eitan ,  Rustom Irani ,  Assaf Shappir

IPC分类号： G11C16/06 ,  H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/105 ,  Y10T29/49002

摘要： A non-volatile memory chip has word lines spaced a sub-F (sub-minimum feature size F) width apart with extensions of the word lines in at least two transition areas. Neighboring extensions are spaced at least F apart. The present invention also includes a method for word-line patterning of a non-volatile memory chip which includes generating sub-F word lines with extensions in transition areas for connecting to peripheral transistors from mask generated elements with widths of at least F.

摘要翻译： 非易失性存储器芯片具有与至少两个过渡区域中的字线的扩展分开的子F（子最小特征尺寸F）宽度的字线。 相邻的延伸部分间隔至少F。 本发明还包括一种用于非易失性存储器芯片的字线图案化的方法，该方法包括在具有至少为F的宽度的掩模生成元件中生成具有用于连接到外围晶体管的过渡区域中的扩展的子F字线。

公开(公告)号：US20070200180A1

公开(公告)日：2007-08-30

申请号：US11646430

申请日：2006-12-28

申请人： Rustom Irani ,  Boaz Eitan ,  Ilan Bloom ,  Assaf Shappir

发明人： Rustom Irani ,  Boaz Eitan ,  Ilan Bloom ,  Assaf Shappir

IPC分类号： H01L29/76

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/11573

摘要： An NVM cell such as an NROM cell is formed using a portion of one ONO stack and an adjacent portion of a neighboring NROM stack. A gate structure is formed between (and atop) the two ONO portions, or “strips” (or “stripes”). This provides having two physically separated charge storage regions (nitride “strips”, or “stripes”) in each memory cell.

摘要翻译： 使用一个ONO堆栈的一部分和相邻NROM堆栈的相邻部分来形成诸如NROM单元的NVM单元。 在（和顶部）两个ONO部分或“条带”（或“条纹”）之间形成栅极结构。 这提供了在每个存储单元中具有两个物理分离的电荷存储区域（氮化物“条带”或“条纹”）。

公开(公告)号：US20080266954A1

公开(公告)日：2008-10-30

申请号：US12213620

申请日：2008-06-23

申请人： Boaz Eitan ,  Rustom Irani ,  Assaf Shappir

发明人： Boaz Eitan ,  Rustom Irani ,  Assaf Shappir

IPC分类号： G11C16/04 ,  H01S4/00

CPC分类号： H01L27/11568 ,  H01L27/105 ,  Y10T29/49002

摘要： A non-volatile memory chip has word lines spaced a sub-F (sub-minimum feature size F) width apart with extensions of the word lines in at least two transition areas. Neighboring extensions are spaced at least F apart. The present invention also includes a method for word-line patterning of a non-volatile memory chip which includes generating sub-F word lines with extensions in transition areas for connecting to peripheral transistors from mask generated elements with widths of at least F.