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Patent Agency Ranking
公开(公告)号：US20220301616A1
公开(公告)日：2022-09-22
申请号：US17206090
申请日：2021-03-18
Inventor： Shu-Han Nien
IPC: G11C11/4093 , H03F3/45 , H03F1/02
Abstract: An amplifier with an input stage comprising: a first current mirror; a first input differential pair; a first current source; a second current source; a second input differential pair, wherein the first input differential pair and the second input differential pair receive a reference voltage; a second current mirror; and a voltage control transmission circuit. An extra current path in the first current mirror is formed and a current flowing through the extra current path flows through the second current mirror to a ground when the reference voltage is higher than a first predetermined value. Also, an extra current path in the second current mirror is formed and a current flowing through the extra current path in the second current mirror flows to the first current mirror when the reference voltage is lower than a second predetermined value.
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公开(公告)号：US11742856B2
公开(公告)日：2023-08-29
申请号：US17535725
申请日：2021-11-26
Inventor： Shu-Han Nien
IPC: H03K19/003 , H03K19/00 , G11C7/10
CPC classification number: H03K19/00384 , H03K19/0027 , G11C7/1057 , G11C7/1084
Abstract: A digital buffer device with self-calibration includes a first buffer circuit, detection circuit, and calibration circuit. The first buffer circuit has a buffer input terminal for receiving an input signal and a buffer output terminal as output of the digital buffer device. The detection circuit includes at least one second buffer circuit for receiving at least one reference signal and generating at least one detection signal to indicate circuit characteristic variations of the at least one second buffer circuit. The at least one second buffer circuit is of a same type of buffer as the first buffer circuit. The calibration circuit has a calibration input terminal for receiving the input signal, and a calibration output terminal coupled to the buffer output terminal. The calibration circuit is for calibrating the first buffer circuit to generate an output signal according to the input signal and the at least one detection signal.
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公开(公告)号：US11942950B2
公开(公告)日：2024-03-26
申请号：US17847225
申请日：2022-06-23
Inventor： Shu-Han Nien
CPC classification number: H03K5/135 , H03K5/2418 , H03K5/2427 , H03K2005/00176
Abstract: An input clock buffer, comprising: a first capacitor; a second capacitor; a first amplifier, configured to generate a first output signal, comprising input terminals coupled to the first capacitor and the second capacitor, wherein the first capacitor and the second capacitor receives a differential input signal; a second amplifier, configured to generate a second output signal according to the differential input signal; a frequency detection circuit, configured to generate a frequency detection signal according to a frequency of the differential input signal; and a switch, located between an output of the first amplifier and an output of the second amplifier, configured to turn on and turn off according to the frequency detection signal.
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公开(公告)号：US11514975B2
公开(公告)日：2022-11-29
申请号：US17206090
申请日：2021-03-18
Inventor： Shu-Han Nien
IPC: G11C11/4093 , H03F3/45 , H03F1/02
Abstract: An amplifier with an input stage comprising: a first current mirror; a first input differential pair; a first current source; a second current source; a second input differential pair, wherein the first input differential pair and the second input differential pair receive a reference voltage; a second current mirror; and a voltage control transmission circuit. An extra current path in the first current mirror is formed and a current flowing through the extra current path flows through the second current mirror to a ground when the reference voltage is higher than a first predetermined value. Also, an extra current path in the second current mirror is formed and a current flowing through the extra current path in the second current mirror flows to the first current mirror when the reference voltage is lower than a second predetermined value.
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公开(公告)号：US20230421143A1
公开(公告)日：2023-12-28
申请号：US17847225
申请日：2022-06-23
Inventor： Shu-Han Nien
CPC classification number: H03K5/135 , H03K5/2427 , H03K5/2418 , H03K2005/00176
Abstract: An input clock buffer, comprising: a first capacitor; a second capacitor; a first amplifier, configured to generate a first output signal, comprising input terminals coupled to the first capacitor and the second capacitor, wherein the first capacitor and the second capacitor receives a differential input signal; a second amplifier, configured to generate a second output signal according to the differential input signal; a frequency detection circuit, configured to generate a frequency detection signal according to a frequency of the differential input signal; and a switch, located between an output of the first amplifier and an output of the second amplifier, configured to turn on and turn off according to the frequency detection signal.
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