公开(公告)号：US20040251401A1

公开(公告)日：2004-12-16

申请号：US10887760

申请日：2004-07-09

Inventor： Daisuke Watanabe

IPC: H01J040/14 ,  G01J001/34

CPC classification number: G11C29/56012 ,  G01R31/31922 ,  H03K5/08 ,  H03K5/13 ,  H03K5/133 ,  H03K2005/00019 ,  H03K2005/00156 ,  H03K2005/00176

Abstract: A delay circuit for delaying an input signal with a desired delay and outputting the delayed signal. The delay circuit includes a light emitting element for emitting light according to an input signal and outputting a delay signal, a bias current source for supplying in advance a first light emitting element with a bias current smaller than a light emission threshold current of the first light emitting element, a bias current controller for controlling the bias current according to a desired delay time, a modulation current source for supplying the light emitting element with a modulation current for making the light emitting element emit light in accordance with the input signal, and a modulation current controller for controlling the modulation current in accordance with a delay resolution in the delay circuit. The modulation current controller controls the modulation current further according to a variable delay range in the delay circuit.

Abstract translation: 一种用于以期望的延迟延迟输入信号并输出​​延迟信号的延迟电路。 延迟电路包括用于根据输入信号发射光并输出延迟信号的发光元件，用于预先向第一发光元件提供小于第一光的发光阈值电流的偏置电流的偏置电流源 发光元件，用于根据期望的延迟时间控制偏置电流的偏置电流控制器，用于向发光元件提供用于使发光元件根据输入信号发光的调制电流的调制电流源，以及 调制电流控制器，用于根据延迟电路中的延迟分辨率来控制调制电流。 调制电流控制器根据延迟电路中的可变延迟范围进一步控制调制电流。

公开(公告)号：US20040056698A1

公开(公告)日：2004-03-25

申请号：US10256099

申请日：2002-09-25

Inventor： Ken Elliott ,  Susan Morton ,  Mark Rodwell

IPC: H03K003/00

CPC classification number: H03K17/603 ,  H03K5/131 ,  H03K17/6264 ,  H03K2005/00065 ,  H03K2005/00176

Abstract: Disclosed is a time delay generator 200 apparatus and method. The apparatus includes a time delay gate 212, a mixer 216 (a Gilbert cell circuit), and a current digital to analog converter 206. The mixer 216, comprised of first and second transistor differential pairs 218 and 220, receives an analog input signal 202 without a delay as well as a delayed input signal 210 produced by the time gate delay. The digital to analog converter regulates the relative current flow between a first control signal 232 and a second control signal 238, effectively altering the mixing of the undelayed input signal 208 and the delayed input signal 210 to generate a delayed output signal 214 with a time or phase delay substantially equal to the temporal delay represented by the digital signal input 204. The time delay generator exhibits reduced phase noise and a linear time delay response.

Abstract translation: 公开了一种时间延迟发生器200的装置和方法。 该装置包括时间延迟门212，混合器216（吉尔伯特单元电路）和当前数模转换器206.由第一和第二晶体管差分对218和220组成的混频器216接收模拟输入信号202 没有延迟，以及由时间门延迟产生的延迟输入信号210。 数模转换器调节第一控制信号232和第二控制信号238之间的相对电流，有效地改变未延迟的输入信号208和延迟输入信号210的混合，以产生具有时间的延迟的输出信号214，或者 相位延迟基本上等于由数字信号输入204表示的时间延迟。时间延迟发生器表现出降低的相位噪声和线性时间延迟响应。

公开(公告)号：US5306971A

公开(公告)日：1994-04-26

申请号：US917386

申请日：1992-07-23

Applicant: Earl McCune

Inventor： Earl McCune

IPC: H03K5/00 ,  H03K5/13

CPC classification number: H03K5/131 ,  H03K2005/00097 ,  H03K2005/00176 ,  H03K2005/00182 ,  H03K2005/00228

Abstract: An electronic, binary-controlled digital tapped delay line is realized by a plurality of like stages connected in cascade. Each stage comprises a differential amplifier circuit responsive to a pair of input signals for producing a pair of output signals and including a differential transistor pair. A first loading circuit formed by a plurality of load devices interconnected to produce a cumulative loading effect is connected to an input of a first transistor of the differential transistor pair for delaying turn-on of the first transistor. Similarly, a second loading circuit formed by a plurality of load devices interconnected to produce a cumulative loading is connected to an input of a second transistor of the differential transistor pair for delaying turn-on of the second transistor, the first and second loading circuits each being connected to a first circuit node. A delay control circuit is responsive to a binary control signal and connected to the first circuit node for causing turn-on of the first and second transistors to be delayed by a set amount of time when the binary control signal is asserted.

Abstract translation: 电子二进制控制数字抽头延迟线通过级联连接的多个相似级来实现。 每个级包括响应于一对输入信号的差分放大器电路，用于产生一对输出信号并且包括差分晶体管对。 由互连以产生累积负载效应的多个负载装置形成的第一负载电路连接到差分晶体管对的第一晶体管的输入，用于延迟第一晶体管的导通。 类似地，由互连以产生累积负载的多个负载装置形成的第二负载电路连接到差分晶体管对的第二晶体管的输入，用于延迟第二晶体管的导通，第一和第二负载电路各自 连接到第一电路节点。 延迟控制电路响应于二进制控制信号并连接到第一电路节点，用于当二进制控制信号被断言时使第一和第二晶体管的导通被延迟设定的时间量。

公开(公告)号：US5066877A

公开(公告)日：1991-11-19

申请号：US662502

申请日：1991-02-28

Applicant: Hiroshi Hamano ,  Izumi Amemiya ,  Takuji Yamamoto ,  Yasunari Arai ,  Takeshi Ihara

Inventor： Hiroshi Hamano ,  Izumi Amemiya ,  Takuji Yamamoto ,  Yasunari Arai ,  Takeshi Ihara

IPC: H03K5/00 ,  H03K5/13

CPC classification number: H03K5/13 ,  H03K5/133 ,  H03K2005/00156 ,  H03K2005/00176 ,  H03K2005/00182

Abstract: A data delay circuit includes a first transistor, and a second transistor having a base, an emitter and a collector. Input data is applied to the bases of the first and second transistors. A constant-current source is coupled between the emitters of the first and second transistors and a negative power source. A capacitor is connected between the collector of the first transistor and the collector of the second transistor. The data delay circuit further includes a third transistor and a fourth transistor. The emitters of the third and fourth transistors are connected to the collectors of the first and second transistors, respectively. The bases of the third and fourth transistors are provided with control data having a polarity opposite to that of the input data and having an adjusted amplitude level corresponding to a desired delay time to be given the input data. First and second load resistors are respectively coupled to the collectors of the third and fourth transistors through a positive power source. Delayed input data is drawn from the collectors of the third and fourth transistors.

Abstract translation: 数据延迟电路包括第一晶体管和具有基极，发射极和集电极的第二晶体管。 输入数据被施加到第一和第二晶体管的基极。 恒流源耦合在第一和第二晶体管的发射极和负电源之间。 电容器连接在第一晶体管的集电极和第二晶体管的集电极之间。 数据延迟电路还包括第三晶体管和第四晶体管。 第三和第四晶体管的发射极分别连接到第一和第二晶体管的集电极。 第三和第四晶体管的基极设置有与输入数据的极性相反的极性的控制数据，并且具有对应于要给予输入数据的所需延迟时间的调整幅度电平。 第一和第二负载电阻器通过正电源分别耦合到第三和第四晶体管的集电极。 来自第三和第四晶体管的集电极的延迟输入数据。

公开(公告)号：US4795923A

公开(公告)日：1989-01-03

申请号：US125022

申请日：1987-11-25

Applicant: Laszlo J. Dobos

Inventor： Laszlo J. Dobos

IPC: H03H11/26 ,  H03K5/00 ,  H03K5/13 ,  H03K17/60 ,  H03K17/62 ,  H03K19/003 ,  H03K17/28

CPC classification number: H03K17/603 ,  H03K17/6264 ,  H03K19/00323 ,  H03K5/13 ,  H03K2005/00052 ,  H03K2005/00176 ,  H03K2005/00182 ,  H03K2005/00228

Abstract: A delay element for producing an output signal in response to a change in state of an input signal includes variable gain first and second amplifiers and a delay buffer having a fixed delay. The input signal is applied as input to the first amplifier and the delay buffer while the output of the delay buffer is applied as input to the second amplifier. The outputs of the first and second amplifiers are summed to provide the output signal. When the gain of the first amplifier is high and the gain of the second amplifier is low, the output signal will respond to the change in state of the input signal with minimum delay. When the gain of the first amplifier is low and the gain of the second amplifier is high, the output signal will respond to the change in state of the input signal with maximum delay. The delay in change of state of the output signal in response to a change of state in the input signal may be adjusted with high resolution to a time intermediate between the minimum and maximum delays by adjusting the gains of the first and second amplifiers.

公开(公告)号：US4565976A

公开(公告)日：1986-01-21

申请号：US520876

申请日：1983-08-05

Applicant: David L. Campbell

Inventor： David L. Campbell

IPC: H03B5/02 ,  G01R29/02 ,  H03K3/03 ,  H03K3/282 ,  H03K3/70 ,  H03K5/00 ,  H03K9/06 ,  H03K19/086 ,  H03L7/07 ,  H03L7/08 ,  H03L7/099 ,  H03M5/12 ,  H04L25/49 ,  H03B1/00

CPC classification number: H03K3/0315 ,  H03K3/70 ,  H03K9/06 ,  H03L7/07 ,  H03L7/0995 ,  H03K2005/00097 ,  H03K2005/00176 ,  Y10S331/03

Abstract: The fall-time of an ECL gate is precisely controlled using a fixed capacitor, which is connected between the positive supply voltage and the ECL gate output terminal, and a variable current source connected between ground and the ECL gate output terminal. A time-delay circuit is obtained by controlling the variable current source with an error voltage of a phase-locked loop such that the time-delay precisely tracks the frequency of the reference signal for the phase-locked loop. A signal detector circuit is obtained by combining time-delay circuits. A voltage-controlled oscillator is assembled by connecting 3 ECL gates with controlled fall-times in a ring oscillator configuration. Addition of a non-inverting input to one ECL gate makes the voltage-controlled oscillator interruptible. Combining a voltage-controlled oscillator of the type described with a phase detector fed by a reference signal provides a phase-locked loop with the control voltage thereof providing a frequency-to-voltage conversion function. A system for providing a receiver clock reference signal from a received signal is provided by phase-locking the output signal of a first phase-locked loop to a system reference signal to generate a first-loop control voltage. A second phase-locked loop is phase-locked to the received signal with a second-loop control voltage. In addition, the second phase-locked loop is also frequency-locked to the system reference signal by the first-loop control voltage. This system is particularly useful for recovering a receiver clock reference from a Manchester-encoded signal.

Abstract translation: 使用连接在正电源电压和ECL栅极输出端子之间的固定电容器以及连接在地和ECL门输出端子之间的可变电流源来精确地控制ECL门的下降时间。 通过用锁相环的误差电压控制可变电流源，使得延时精确跟踪用于锁相环的参考信号的频率来获得时间延迟电路。 通过组合时间延迟电路获得信号检测器电路。 通过在环形振荡器配置中连接3个ECL门和受控的下降时间来组装压控振荡器。 将一个非反相输入添加到一个ECL门使得压控振荡器可以中断。 将所描述类型的压控振荡器与由参考信号馈送的相位检测器相结合，提供锁相环，其控制电压提供频率 - 电压转换功能。 通过将第一锁相环的输出信号锁定到系统参考信号以产生第一回路控制电压来提供从接收信号提供接收器时钟参考信号的系统。 第二个锁相环与第二回路控制电压的接收信号锁相。 此外，第二个锁相环也通过第一回路控制电压对系统参考信号进行频率锁定。 该系统对于从曼彻斯特编码的信号恢复接收机时钟参考特别有用。

公开(公告)号：US06417712B1

公开(公告)日：2002-07-09

申请号：US09669874

申请日：2000-09-27

Applicant: R. Douglas Beards ,  John J. Nisbet ,  Qi Tang ,  Eric Gagnon

Inventor： R. Douglas Beards ,  John J. Nisbet ,  Qi Tang ,  Eric Gagnon

IPC: H03K513

CPC classification number: H03H11/22 ,  H03C3/40 ,  H03H11/24 ,  H03K2005/00169 ,  H03K2005/00176 ,  H03K2005/00286

Abstract: Sine and cosine weighting functions are applied to phase quadrature versions of an input signal to be phase shifted, and the weighted results are summed to provide a phase shifted output signal with an amplitude which is relatively independent of the phase shift. A weighting circuit comprises two translinear sine shaping circuits having differential current outputs providing weighting signals from input currents supplied thereto, the input currents of the two sine shaping circuits being offset relative to one another so that the differential current outputs of the two sine shaping circuits are provided in accordance with a sine function and a cosine function, respectively, of a control signal.

Abstract translation: 正弦和余弦加权函数被应用于要相移的输入信号的相位正交版本，并且将加权结果相加以提供具有相对独立于相移的幅度的相移输出信号。 一个加权电路包括两个具有差分电流输出的交叉线性正弦整形电路，该电流输出从提供给其的输入电流提供加权信号，两个正弦整形电路的输入电流相对于彼此偏移，使得两个正弦整形电路的差分电流输出为 分别根据控制信号的正弦函数和余弦函数提供。

公开(公告)号：US06288588B1

公开(公告)日：2001-09-11

申请号：US09479338

申请日：2000-01-07

Applicant: Arnold M. Frisch

Inventor： Arnold M. Frisch

IPC: H03H1120

CPC classification number: H03K5/133 ,  H03H11/265 ,  H03K2005/00026 ,  H03K2005/00176

Abstract: A programmable delay circuit employs a relatively slow conventional silicon emitter-coupled transistor pair and a relatively fast silicon/germanium heterojunction emitter-coupled transistor pair. The bases of both transistor pairs are driven by an input signal to be delayed. The collectors of transistors of both pairs are linked to a voltage source through a pair of load resistors, with an output signal appearing across the collectors of both transistor pairs. A current source draws complementary adjustable load currents through the two transistor pairs. Although the sum of the two load currents is a constant, the relative amount of load current drawn though the two transistor pairs is adjustable. The silicon transistors have a substantially lower peak Ft than the silicon/germanium transistors, and the sum of the load currents the current source draws through the collector-emitter paths of the transistor pairs is selected so that when the silicon/germanium transistor pair conducts all of the load current they operate near their peak Ft and switch near their maximum speed. However when the silicon transistor pair conducts all of the load current, the silicon transistors operate substantially below their peak Ft and therefore switch at much less than their maximum speed. The delay between state changes in the input and output signals is determined by the relative amount of load current supplied to each transistor pair.

Abstract translation: 可编程延迟电路使用相对较慢的常规硅发射极耦合晶体管对和相对较快的硅/锗异质结发射极耦合晶体管对。 两个晶体管对的基极由要延迟的输入信号驱动。 两对晶体管的集电极通过一对负载电阻器连接到电压源，输出信号出现在两个晶体管对的集电极上。 电流源通过两个晶体管对提供互补的可调负载电流。 尽管两个负载电流之和是一个常数，但是通过两个晶体管对拉出的负载电流的相对量是可调节的。 硅晶体管具有比硅/锗晶体管更低的峰值Ft，并且选择电流源通过晶体管对的集电极 - 发射极路径的负载电流之和，使得当硅/锗晶体管对导通全部时 的负载电流，它们在峰值Ft附近工作，并在其最大速度附近切换。 然而，当硅晶体管对导通所有负载电流时，硅晶体管的工作电压基本上低于其峰值Ft，因此开关远小于其最大速度。 输入和输出信号的状态变化之间的延迟由提供给每个晶体管对的负载电流的相对量决定。

公开(公告)号：US06222423B1

公开(公告)日：2001-04-24

申请号：US09244279

申请日：1999-02-03

Applicant: Douglas Sudjian

Inventor： Douglas Sudjian

IPC: H03B502

CPC classification number: H03K5/133 ,  H03K2005/00026 ,  H03K2005/00071 ,  H03K2005/00176

Abstract: A delay cell for use within a voltage controlled oscillator capable of operating at two different selectable frequencies, the delay cell having a first delay stage including a first differential pair of transistors, wherein the emitter or each transistor is coupled to a first common node and further wherein a first current exiting the first common node is selectively variable. The delay cell further having a second delay stage including a second differential pair of transistors, each having an emitter coupled to a second common node wherein a second current exiting the second common node is selectively variable and wherein a sum of the first current and the second current is substantially constant. The amount of delay associated with the first delay stage is dependent upon the level of the first current. The delay cell provides for a more linear relationship between output frequency and input voltage by controlling the first current through the first delay stage and the second current through the second delay stage such that a decrease in the first current is accompanied by an increase in the second current and, conversely, an increase in the first current is accompanied by a decrease in the second current and the sum of the first current and second current is substantially constant.

Abstract translation: 一种用于能够在两个不同可选频率下运行的压控振荡器内的延迟单元，所述延迟单元具有包括第一差分对晶体管的第一延迟级，其中所述发射极或每个晶体管耦合到第一公共节点，并且进一步地 其中离开所述第一公共节点的第一电流是有选择地变化的。 所述延迟单元还具有包括第二差分对晶体管的第二延迟级，每个晶体管具有耦合到第二公共节点的发射极，其中离开所述第二公共节点的第二电流是有选择地变化的，并且其中所述第一电流和第二 电流基本恒定。 与第一延迟阶段相关联的延迟量取决于第一电流的电平。 延迟单元通过控制通过第一延迟级的第一电流和通过第二延迟级的第二电流来提供输出频率和输入电压之间的更线性关系，使得第一电流的减小伴随着第二电流的增加 而相反地，第一电流的增加伴随着第二电流的减小，并且第一电流和第二电流的总和基本上是恒定的。

公开(公告)号：US5461335A

公开(公告)日：1995-10-24

申请号：US946721

申请日：1992-09-18

Applicant: Chikara Tsuchiya

Inventor： Chikara Tsuchiya

IPC: H03H11/26 ,  H03H11/04 ,  H03K5/00 ,  H03K5/13 ,  H03K5/159

CPC classification number: H03K5/13 ,  H03H11/04 ,  H03K5/133 ,  H03K2005/00176

Abstract: A delay circuit includes a first filter circuit responsive to an input signal and outputting a first output signal having first-order low pass characteristics with respect to the input signal, a second filter circuit responsive to the input signal and outputting a second output signal having first-order high pass characteristics with respect to the input signal, and a difference computing circuit responsive to the first and second output signals and outputting a difference signal therebetween as an output signal of the delay circuit. By the constitution, it is possible to reduce an attenuation factor irrespective of the input signal frequency and obtain a relatively long and easily changeable delay time in a wide frequency band.

Abstract translation: 延迟电路包括响应于输入信号并输出​​相对于输入信号具有一阶低通特性的第一输出信号的第一滤波器电路，响应于输入信号的第二滤波器电路，并输出具有第一输出信号的第二输出信号 以及差分计算电路，响应于第一和第二输出信号，并输出它们之间的差分信号作为延迟电路的输出信号。 通过该结构，可以与输入信号频率无关地减小衰减因子，并获得宽频带中较长且容易变化的延迟时间。