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1.发明申请Efficient advanced encryption standard (AES) Datapath using hybrid rijndael S-Box 失效高效的高级加密标准（AES）使用混合rijndael S-Box的数据路径公开(公告)号：US20080240422A1
公开(公告)日：2008-10-02
申请号：US11731159
申请日：2007-03-30
申请人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali , Kirk S. Yap
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali , Kirk S. Yap
IPC分类号： H04L9/00
CPC分类号： H04L9/0631 , G06F9/30007 , H04L2209/12
摘要： The speed at which an AES decrypt operation may be performed in a general purpose processor is increased by providing a separate decrypt data path. The critical path delay of the aes decrypt path is reduced by combining multiply and inverse operations in the Inverse SubBytes transformation. A further decrease in critical path delay in the aes decrypt data path is provided by merging appropriate constants of the inverse mix-column transform into a map function.
摘要翻译： 可以通过提供单独的解密数据路径来增加在通用处理器中执行AES解密操作的速度。 通过在逆SubBytes变换中组合乘法和逆运算来减少aes解密路径的关键路径延迟。 通过将反混合列变换的适当常数合并到映射函数中来提供aes解密数据路径中关键路径延迟的进一步减小。
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2.发明申请公开(公告)号：US20080240421A1
公开(公告)日：2008-10-02
申请号：US11731158
申请日：2007-03-30
申请人： Vinodh Gopal , Erdinc Ozturk , Gilbert Wolrich , Wajdi K. Feghali , Kirk S. Yap
发明人： Vinodh Gopal , Erdinc Ozturk , Gilbert Wolrich , Wajdi K. Feghali , Kirk S. Yap
IPC分类号： H04L9/00
CPC分类号： H04L9/0631 , G06F9/30007 , H04L2209/125
摘要： The speed at which encrypt and decrypt operations may be performed in a general purpose processor is increased by providing a separate encrypt data path and decrypt data path. With separate data paths, each of the data paths may be individually optimized in order to reduce delays in a critical path. In addition, delays may be hidden in a non-critical last round.
摘要翻译： 可以通过提供单独的加密数据路径和解密数据路径来增加在通用处理器中执行加密和解密操作的速度。 利用单独的数据路径，可以单独优化每个数据路径以减少关键路径中的延迟。 此外，延迟可能隐藏在非关键的最后一轮。
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3.发明授权Efficient advanced encryption standard (AES) datapath using hybrid rijndael S-box 失效使用混合rijndael S盒的高效加密标准（AES）数据通路公开(公告)号：US08346839B2
公开(公告)日：2013-01-01
申请号：US11731159
申请日：2007-03-30
申请人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali , Kirk S. Yap
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali , Kirk S. Yap
IPC分类号： G06F7/52
CPC分类号： H04L9/0631 , G06F9/30007 , H04L2209/12
摘要： The speed at which an AES decrypt operation may be performed in a general purpose processor is increased by providing a separate decrypt data path. The critical path delay of the aes decrypt path is reduced by combining multiply and inverse operations in the Inverse SubBytes transformation. A further decrease in critical path delay in the aes decrypt data path is provided by merging appropriate constants of the inverse mix-column transform into a map function.
摘要翻译： 可以通过提供单独的解密数据路径来增加在通用处理器中执行AES解密操作的速度。 通过在逆SubBytes变换中组合乘法和逆运算来减少aes解密路径的关键路径延迟。 通过将反混合列变换的适当常数合并到映射函数中来提供aes解密数据路径中关键路径延迟的进一步减小。
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4.发明授权公开(公告)号：US08391475B2
公开(公告)日：2013-03-05
申请号：US11731158
申请日：2007-03-30
申请人： Vinodh Gopal , Erdinc Ozturk , Gilbert Wolrich , Wajdi K. Feghali , Kirk S. Yap
发明人： Vinodh Gopal , Erdinc Ozturk , Gilbert Wolrich , Wajdi K. Feghali , Kirk S. Yap
IPC分类号： H04K1/00
CPC分类号： H04L9/0631 , G06F9/30007 , H04L2209/125
摘要： The speed at which encrypt and decrypt operations may be performed in a general purpose processor is increased by providing a separate encrypt data path and decrypt data path. With separate data paths, each of the data paths may be individually optimized in order to reduce delays in a critical path. In addition, delays may be hidden in a non-critical last round.
摘要翻译： 可以通过提供单独的加密数据路径和解密数据路径来增加在通用处理器中执行加密和解密操作的速度。 利用单独的数据路径，可以单独优化每个数据路径以减少关键路径中的延迟。 此外，延迟可能隐藏在非关键的最后一轮。
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公开(公告)号：US20080304659A1
公开(公告)日：2008-12-11
申请号：US11760733
申请日：2007-06-08
申请人： Erdinc Ozturk , Kirk S. Yap , Gilbert Wolrich , Wajdi K. Feghali , Vinodh Gopal
发明人： Erdinc Ozturk , Kirk S. Yap , Gilbert Wolrich , Wajdi K. Feghali , Vinodh Gopal
IPC分类号： H04L9/28
CPC分类号： H04L9/0631 , G06F9/30007 , H04L2209/12 , H04L2209/24
摘要： A key scheduler performs a key-expansion to generate round keys for AES encryption and decryption just-in-time for each AES round. The key scheduler pre-computes slow operations in a current clock cycle to reduce the critical delay path for computing the round key for a next AES round.
摘要翻译： 密钥调度程序执行密钥扩展，以便为每个AES轮次准时生成AES加密和解密的循环密钥。 密钥调度器在当前时钟周期内预先计算慢速操作，以减少用于计算下一个AES循环的循环密钥的关键延迟路径。
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公开(公告)号：US08520845B2
公开(公告)日：2013-08-27
申请号：US11760733
申请日：2007-06-08
申请人： Erdinc Ozturk , Kirk S. Yap , Gilbert Wolrich , Wajdi K. Feghali , Vinodh Gopal
发明人： Erdinc Ozturk , Kirk S. Yap , Gilbert Wolrich , Wajdi K. Feghali , Vinodh Gopal
IPC分类号： H04L9/00
CPC分类号： H04L9/0631 , G06F9/30007 , H04L2209/12 , H04L2209/24
摘要： A key scheduler performs a key-expansion to generate round keys for AES encryption and decryption just-in-time for each AES round. The key scheduler pre-computes slow operations in a current clock cycle to reduce the critical delay path for computing the round key for a next AES round.
摘要翻译： 密钥调度程序执行密钥扩展，以便为每个AES轮次准时生成AES加密和解密的循环密钥。 密钥调度器在当前时钟周期内预先计算慢速操作，以减少用于计算下一个AES循环的循环密钥的关键延迟路径。
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公开(公告)号：US09419792B2
公开(公告)日：2016-08-16
申请号：US13730216
申请日：2012-12-28
CPC分类号： H04W12/02 , G06F9/30007 , G06F9/30036 , G06F9/30134 , G06F9/3887 , G09C1/00 , H04L9/065 , H04L9/0668 , H04L63/045 , H04L63/0457 , H04W12/04
摘要： Vector instructions for performing SNOW 3G wireless security operations are received and executed by the execution circuitry of a processor. The execution circuitry receives a first operand of the first instruction specifying a first vector register that stores a current state of a finite state machine (FSM). The execution circuitry also receives a second operand of the first instruction specifying a second vector register that stores data elements of a liner feedback shift register (LFSR) that are needed for updating the FSM. The execution circuitry executes the first instruction to produce a updated state of the FSM and an output of the FSM in a destination operand of the first instruction.
摘要翻译： 用于执行SNOW 3G无线安全操作的矢量指令由处理器的执行电路接收和执行。 执行电路接收指定存储有限状态机（FSM）的当前状态的第一向量寄存器的第一指令的第一操作数。 执行电路还接收指定第二向量寄存器的第一指令的第二操作数，该第二指令寄存器存储用于更新FSM所需的线性反馈移位寄存器（LFSR）的数据元素。 执行电路执行第一指令以产生FSM的更新状态和FSM在第一指令的目的地操作数中的输出。
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公开(公告)号：US20140195782A1
公开(公告)日：2014-07-10
申请号：US13976274
申请日：2012-03-30
申请人： Kirk S. Yap , Gilbert M. Wolrich , James D. Guilford , Vinodh Gopal , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
发明人： Kirk S. Yap , Gilbert M. Wolrich , James D. Guilford , Vinodh Gopal , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30007 , G06F9/30036 , G06F9/30058 , G06F9/30098 , G06F9/30145 , G06F9/3802 , G06F9/384 , G06F12/0875 , G06F12/0897 , G06F12/1027 , G06F15/8007 , G06F21/602 , G06F2212/452 , G06F2212/68 , H04L9/0643 , H04L9/3239 , H04L2209/125
摘要： A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.
摘要翻译： 处理器包括指令解码器，用于接收处理安全散列算法2（SHA-2）散列算法的第一指令，所述第一指令具有与第一存储位置相关联的第一操作数，以存储SHA-2状态和第二操作数 与第二存储位置相关联以存储多个消息和回合常数。 处理器还包括执行单元，其耦合到指令解码器，以在由第一操作数和由第二操作数指定的多个消息和循环常数指定的SHA-2状态上执行SHA-2散列算法的一个或多个迭代， 响应第一条指令。
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公开(公告)号：US20140016774A1
公开(公告)日：2014-01-16
申请号：US13992461
申请日：2011-12-22
申请人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , James D. Guilford , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
发明人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , James D. Guilford , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
IPC分类号： H04L9/28
CPC分类号： H04L9/28 , G06F9/30018 , G06F9/30036 , G06F9/30109 , G06F13/14 , H04L9/0631 , H04L9/0643
摘要： A method is described. The method includes executing an instruction to perform one or more Galois Field (GF) multiply by 2 operations on a state matrix and executing an instruction to combine results of the one or more GF multiply by 2 operations with exclusive or (XOR) functions to generate a result matrix.
摘要翻译： 描述了一种方法。 该方法包括执行在状态矩阵上乘以2次操作的一个或多个伽罗瓦域（GF）的指令，并且执行将所述一个或多个GF乘以2个运算的结果与异或（XOR）函数相结合的指令，以产生 一个结果矩阵。
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公开(公告)号：US09632782B2
公开(公告)日：2017-04-25
申请号：US13976274
申请日：2012-03-30
申请人： Kirk S. Yap , Gilbert M. Wolrich , James D. Guilford , Vinodh Gopal , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
发明人： Kirk S. Yap , Gilbert M. Wolrich , James D. Guilford , Vinodh Gopal , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
CPC分类号： G06F9/3016 , G06F9/30007 , G06F9/30036 , G06F9/30058 , G06F9/30098 , G06F9/30145 , G06F9/3802 , G06F9/384 , G06F12/0875 , G06F12/0897 , G06F12/1027 , G06F15/8007 , G06F21/602 , G06F2212/452 , G06F2212/68 , H04L9/0643 , H04L9/3239 , H04L2209/125
摘要： A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.
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