公开(公告)号：US20160337083A1

公开(公告)日：2016-11-17

申请号：US14713632

申请日：2015-05-15

申请人： Eric Englert ,  Bernard Marchand ,  John F. Pillar

发明人： Eric Englert ,  Bernard Marchand ,  John F. Pillar

IPC分类号： H04L1/00 ,  G06F11/10

CPC分类号： H04L1/0061

摘要： A method and apparatus are provided for computing a CRC value for a packet containing a data stream with a modified data unit data and one or more additional data units extending to the end of the data stream by computing a first CRC value from the one or more additional data units, computing a second CRC value from the modified data unit, adjusting the second CRC value based on a shift length equal to a distance of the one or more additional data units to compute a perspective shifted second CRC value by using fixed number of distance lookup table operations, and generating an updated CRC value from the first CRC value and perspective shifted second CRC value, thereby avoiding recalculating a complete CRC value based on an entirety of the modified data stream.

摘要翻译： 提供了一种方法和装置，用于计算包含经修改的数据单元数据的数据流的分组的CRC值，以及通过从所述一个或多个数据流计算第一CRC值而延伸到数据流的结尾的一个或多个附加数据单元 附加数据单元，从修改的数据单元计算第二CRC值，基于等于所述一个或多个附加数据单元的距离的移位长度来调整第二CRC值，以通过使用固定数量的 距离查找表操作，并且从第一CRC值和透视偏移的第二CRC值生成更新的CRC值，从而避免基于整个修改的数据流重新计算完整的CRC值。

公开(公告)号：US09680605B2

公开(公告)日：2017-06-13

申请号：US14713632

申请日：2015-05-15

申请人： Eric Englert ,  Bernard Marchand ,  John F. Pillar

发明人： Eric Englert ,  Bernard Marchand ,  John F. Pillar

IPC分类号： H03M13/00 ,  H04L1/00

CPC分类号： H04L1/0061

摘要： A method and apparatus are provided for computing a CRC value for a data stream packet with a modified portion and an unmodified portion extending a distance to the end of the data stream packet by computing a first CRC value from the unmodified portion, computing a second CRC value from the modified portion, adjusting the second CRC value based on a shift length equal to the distance of the unmodified portion to compute a perspective shifted second CRC value by using a fixed number of distance lookup table operations, and generating an updated CRC value from the first CRC value and perspective shifted second CRC value, thereby avoiding recalculating a complete CRC value based on an entirety of the data stream packet.

公开(公告)号：US06331970B1

公开(公告)日：2001-12-18

申请号：US09220857

申请日：1998-12-28

申请人： Benjamin B. Nieh ,  John F. Pillar ,  Jacob Guttman ,  Bernard Marchand ,  Sameh Rabie

发明人： Benjamin B. Nieh ,  John F. Pillar ,  Jacob Guttman ,  Bernard Marchand ,  Sameh Rabie

IPC分类号： H04L1256

CPC分类号： H04L12/5601 ,  H04L2012/5629 ,  H04L2012/5635 ,  H04L2012/5636

摘要： In an ATM communication system, a source transmitting in accordance with an Available Bit Rate service category must be policed to ensure that the cells are transmitted at a rate within the cell rate specified by the network at any given time. The usage parameter control system can only store a limited number of pending cell transmission rates to be enforced, and must make approximations by discarding certain stored pending cell transmission rates in order to make room for new cell transmission rates. This invention is directed towards a method for selecting which stored cell rates to discard that allows less cheating room in the cell rate enforcement than does the prior art, and that does not over-police.

摘要翻译： 在ATM通信系统中，必须对根据可用比特率服务类别进行发送的源进行监管，以确保以任何给定时间由网络指定的小区速率内的小区发送小区。 使用参数控制系统只能存储要强制执行的有限数量待决小区传输速率，并且必须通过丢弃某些存储的待决小区传输速率来进行近似，以便为新的小区传输速率腾出空间。 本发明涉及一种用于选择哪些存储的信元速率丢弃的方法，其允许比现有技术更少的小区欺骗室，并且不会过警。

公开(公告)号：US09437299B2

公开(公告)日：2016-09-06

申请号：US14230255

申请日：2014-03-31

申请人： Tommi M. Jokinen ,  John F. Pillar

发明人： Tommi M. Jokinen ,  John F. Pillar

IPC分类号： G06F9/50 ,  G11C15/00 ,  G11C7/10

CPC分类号： G11C15/00 ,  G06F9/5038 ,  G11C7/1006

摘要： A data processing system includes a content addressable memory (CAM). Each entry of the CAM corresponds to a task and is configured to store a current scope of each task. A random access memory (RAM) is configured to shadow information of the CAM. Transition position storage circuitry is configured to store transition age positions for tasks. Control circuitry is configured to, in response to a command to transition a selected task to a destination scope, access the RAM to determine the current scope for the selected task, use the current scope to perform a match determination with the CAM to determine if any entries corresponding to tasks other than the selected task match the current scope; and for any matching entries, updating a transition age position in the transition position storage circuitry for the corresponding task within the current scope.

摘要翻译： 数据处理系统包括内容寻址存储器（CAM）。 CAM的每个条目对应于任务，并且被配置为存储每个任务的当前范围。 随机存取存储器（RAM）被配置为阴影CAM的信息。 过渡位置存储电路被配置为存储任务的过渡年龄位置。 控制电路被配置为响应于将所选任务转换到目的地范围的命令，访问RAM以确定所选任务的当前范围，使用当前范围来执行与CAM的匹配确定以确定是否有 与所选任务以外的任务相对应的条目与当前范围相匹配; 并且对于任何匹配的条目，更新用于当前范围内的相应任务的转换位置存储电路中的转换年龄位置。

公开(公告)号：US09785473B2

公开(公告)日：2017-10-10

申请号：US14330331

申请日：2014-07-14

申请人： William C. Moyer ,  John F. Pillar

发明人： William C. Moyer ,  John F. Pillar

IPC分类号： G06F9/46 ,  G06F9/50 ,  G06F9/48

CPC分类号： G06F9/5027 ,  G06F9/4843

摘要： Configurable per-task state counters for processing cores in multi-tasking processing systems are disclosed along with related methods. In part, the disclosed embodiments include a work scheduler and a plurality of processing cores. The work scheduler assigns tasks to the processing cores, and the processing cores concurrently process multiple assigned tasks using a plurality of processing states. Further, task state counters are provided for each assigned task, and these task state counters are incremented for each cycle that the task stays within selected processing states to generate per-task state count values for the assigned tasks. These per-task state count values are reported back to the work scheduler when processing for the task ends. The work scheduler can then use one or more of the per-task state count values to adjust how new tasks are assigned to the processing cores.

公开(公告)号：US07388837B1

公开(公告)日：2008-06-17

申请号：US10422831

申请日：2003-04-25

申请人： Bernard F. St-Denis ,  John F. Pillar ,  Scott S. Larrigan

发明人： Bernard F. St-Denis ,  John F. Pillar ,  Scott S. Larrigan

IPC分类号： G01R31/08

CPC分类号： H04L47/10 ,  H04L47/20 ,  H04L47/21

摘要： The invention provides a method and apparatus for policing a traffic flow in which a first stage of policing is performed on the traffic flow to produce a first stage conforming flow and a first stage violating flow. These two flows are then policed again in a second stage of policing, such that the first stage conforming flow can take advantage of a capacity allowed for the first stage violating flow which is unused by the first stage violating flow. In some embodiments, performing a first stage of policing involves associating each packet of the traffic flow with one of a plurality of sub-flows, policing at least one of the plurality of sub-flows individually to produce for each sub-flow a respective conforming sub-flow and a respective violating sub-flow. The conforming sub-flow(s) collectively are the first stage conforming flow. The violating sub-flows collectively are the first stage violating flow.

摘要翻译： 本发明提供了一种用于管理业务流的方法和装置，其中在业务流上执行第一阶段的监管以产生第一阶段一致流和第一阶段违反流。 然后在第二阶段的监管中再次对这两个流进行监管，使得第一阶段符合流可以利用第一阶段违反流未被使用的第一阶段违反流量允许的容量。 在一些实施例中，执行第一阶段的策略涉及将业务流的每个分组与多个子流中的一个相关联，分别管理多个子流中的至少一个子流，以针对每个子流产生相应的一致 子流和相应的违规子流。 一致的子流程集体是第一阶段符合流程。 违规流动是第一阶段违法流动。

公开(公告)号：US08156265B2

公开(公告)日：2012-04-10

申请号：US12476586

申请日：2009-06-02

申请人： Tim J. Buick ,  John F. Pillar

发明人： Tim J. Buick ,  John F. Pillar

IPC分类号： G06F12/02 ,  G06F3/00

CPC分类号： G06F9/546 ,  G06F2209/548

摘要： A data processor includes a single-token-record memory, a sequence circuit, and a memory controller. The single-token-record memory has a plurality of first storage locations. The sequencer circuit is coupled to the single-token-record memory. The sequencer circuit, responsive to a request to place a token in a tail-end of a queue, either stores said token into one of the plurality of first storage locations if the single-token-record memory stores no greater than a predetermined number of tokens associated with the tail-end of the queue, or stores the token with at least one additional token and a pointer to a next storage location into one of a plurality of second storage locations otherwise. The memory controller is coupled to the sequencer circuit to store the token with the at least one additional token and the pointer in a location of a multi-token-record memory having the plurality of second storage locations.

摘要翻译： 数据处理器包括单令牌记录存储器，序列电路和存储器控制器。 单令牌记录存储器具有多个第一存储位置。 定序器电路耦合到单令牌记录存储器。 如果单令牌记录存储器不存在不大于预定数量的定时器，则定序器电路响应于将令牌放置在队列的尾端中的请求，将所述令牌存储在多个第一存储位置之一中 与队列的尾端相关联的令牌，或将具有至少一个附加令牌的令牌和指向下一个存储位置的指针存储到多个第二存储位置之一，否则。 存储器控制器耦合到定序器电路，以将具有至少一个附加令牌的令牌和指针存储在具有多个第二存储位置的多令牌记录存储器的位置中。

公开(公告)号：US09733981B2

公开(公告)日：2017-08-15

申请号：US14300762

申请日：2014-06-10

申请人： Tommi M. Jokinen ,  Michael Kardonik ,  David B. Kramer ,  Peter W. Newton ,  John F. Pillar ,  Kun Xu

发明人： Tommi M. Jokinen ,  Michael Kardonik ,  David B. Kramer ,  Peter W. Newton ,  John F. Pillar ,  Kun Xu

IPC分类号： G06F9/48 ,  G06F9/46

CPC分类号： G06F9/4881 ,  G06F2209/484

摘要： A data processing system includes a processor core and a hardware module. The processor core performs tasks on data packets. The ordering scope manager stores a first value in a first storage location. The first value indicates that exclusive execution of a first task in a first ordering scope is enabled. In response to a relinquish indicator being received, the ordering scope manager stores a second value in the first storage location. The second value indicates that the exclusively execution of the first task in the first ordering scope is disabled.

公开(公告)号：US20150355938A1

公开(公告)日：2015-12-10

申请号：US14300762

申请日：2014-06-10

申请人： Tommi M. Jokinen ,  Michael Kardonik ,  David B. Kramer ,  Peter W. Newton ,  John F. Pillar ,  Kun Xu

发明人： Tommi M. Jokinen ,  Michael Kardonik ,  David B. Kramer ,  Peter W. Newton ,  John F. Pillar ,  Kun Xu

IPC分类号： G06F9/48

CPC分类号： G06F9/4881 ,  G06F2209/484

摘要： A data processing system includes a processor core and a hardware module. The processor core performs tasks on data packets. The ordering scope manager stores a first value in a first storage location. The first value indicates that exclusive execution of a first task in a first ordering scope is enabled. In response to a relinquish indicator being received, the ordering scope manager stores a second value in the first storage location. The second value indicates that the exclusively execution of the first task in the first ordering scope is disabled.

摘要翻译： 数据处理系统包括处理器核心和硬件模块。 处理器内核在数据包上执行任务。 订购范围管理器将第一个值存储在第一个存储位置。 第一个值表示启用第一个排序范围中的第一个任务的独占执行。 响应于接收到的放弃指示符，订购范围管理器将第二值存储在第一存储位置中。 第二个值表示第一个排序范围中的第一个任务的排他性执行被禁用。

公开(公告)号：US20160011907A1

公开(公告)日：2016-01-14

申请号：US14330331

申请日：2014-07-14

申请人： William C. Moyer ,  John F. Pillar

发明人： William C. Moyer ,  John F. Pillar

IPC分类号： G06F9/50 ,  G06F9/48

CPC分类号： G06F9/5027 ,  G06F9/4843

摘要： Configurable per-task state counters for processing cores in multi-tasking processing systems are disclosed along with related methods. In part, the disclosed embodiments include a work scheduler and a plurality of processing cores. The work scheduler assigns tasks to the processing cores, and the processing cores concurrently process multiple assigned tasks using a plurality of processing states. Further, task state counters are provided for each assigned task, and these task state counters are incremented for each cycle that the task stays within selected processing states to generate per-task state count values for the assigned tasks. These per-task state count values are reported back to the work scheduler when processing for the task ends. The work scheduler can then use one or more of the per-task state count values to adjust how new tasks are assigned to the processing cores.

摘要翻译： 在多任务处理系统中处理核心的可配置的每任务状态计数器与相关方法一起公开。 部分地，所公开的实施例包括工作调度器和多个处理核心。 工作调度器将任务分配给处理核心，并且处理核心使用多个处理状态并发地处理多个分配的任务。 此外，为每个分配的任务提供任务状态计数器，并且对于任务保持在所选处理状态中的每个周期，这些任务状态计数器递增，以为分配的任务生成每任务状态计数值。 当处理任务结束时，这些每任务状态计数值被报告回工作调度程序。 然后，工作调度程序可以使用每个任务状态计数值中的一个或多个来调整如何将新任务分配给处理核心。