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17 条记录 (耗时 0.026 秒)

    Low profile cable connector with hybrid latch
    5.
    发明申请
    Low profile cable connector with hybrid latch 审中-公开
    带混合锁存器的低调电缆连接器

    公开(公告)号：US20050032411A1

    公开(公告)日：2005-02-10

    申请号：US10635107

    申请日：2003-08-06

    申请人： Glen Gutgold ,  Tracy Smith ,  Eric Fischer

    发明人： Glen Gutgold ,  Tracy Smith ,  Eric Fischer

    IPC分类号： H01R13/621 ,  H01R13/627

    CPC分类号： H01R13/6275 ,  H01R13/621

    摘要： A low profile cable connector includes a mating connector face, and first and second lateral sides extending from said mating connector face. One of the first and second sides comprises a bail latch retainer thereon, and a jack screw latch is located adjacent the other of said first and second sides. The cable exit extends from one of the first and second sides at an angle to the mating connector face. The bail latch retainer comprises a bail latch slot, and the jack screw extends through a top surface of the connector. The connector is defined by first and second backshells joined to one another.

    摘要翻译： 小型电缆连接器包括配合连接器面，以及从所述配合连接器面延伸的第一和第二侧面。 第一和第二侧中的一个在其上包括一个吊环闩锁保持器，并且千斤顶螺丝锁定件邻近所述第一和第二侧面中的另一侧定位。 电缆出口从第一和第二侧中的一个以与配合连接器面成一定角度延伸。 吊钩闩锁保持器包括吊环闩锁槽，并且插座螺钉延伸穿过连接器的顶表面。 连接器由彼此连接的第一和第二后壳限定。

    Optimize global net timing with repeater buffers
    6.
    发明授权
    Optimize global net timing with repeater buffers 失效
    使用中继缓冲区优化全局网络时序

    公开(公告)号：US06684373B1

    公开(公告)日：2004-01-27

    申请号：US09620504

    申请日：2000-07-20

    申请人： Franklin Bodine ,  Eric Fischer ,  Tom Arneberg ,  David Poli

    发明人： Franklin Bodine ,  Eric Fischer ,  Tom Arneberg ,  David Poli

    IPC分类号： G06F1750

    CPC分类号： G06F17/505

    摘要： A method, system, and program product for designing an electronic circuit. The electronic circuit has a source component, a sink component and a wire connecting the source and sink components. In one aspect, the wire is divided into wire segments and repeater buffers are added to connect the wire segments. The number of repeater buffers is based on the calculated delay of the global net. In another aspect, the metal routes of the wire are widened to reduce delays on a global net. In these ways, the timing goal of the electronic circuit is met, such that an operation in the electronic circuit will complete within one clock cycle.

    摘要翻译： 一种用于设计电子电路的方法，系统和程序产品。 电子电路具有源组件，宿组件和连接源组件和宿组件的电线。 在一个方面，线被分成线段，并且添加中继器缓冲器以连接线段。 中继器缓冲器的数量基于计算出的全局网络的延迟。 另一方面，电线的金属线路被加宽以减少全球网络的延迟。 以这些方式，满足电子电路的时序目标，使得电子电路中的操作将在一个时钟周期内完成。

    Device and method for accurately determining the rear vertex distance between the eye and the lenses in eyeglasses
    8.
    发明授权
    Device and method for accurately determining the rear vertex distance between the eye and the lenses in eyeglasses 有权
    用于准确地确定眼睛与眼镜之间的眼睛与镜片之间的后顶点距离的装置和方法

    公开(公告)号：US08857986B2

    公开(公告)日：2014-10-14

    申请号：US12430073

    申请日：2009-04-25

    申请人： Eric Fischer

    发明人： Eric Fischer

    IPC分类号： A61B3/14 ,  G02C5/00 ,  A61B3/11 ,  G02C13/00

    CPC分类号： G02C13/005 ,  A61B3/11

    摘要： A measurement instrument and its associated method of use to record a pupil center position of a person's eye and determine rear vertex distance to a lens. The instrument has a chassis and a free swinging assembly that is pivotably attached to the chassis. The swinging assembly has alignment points that remain in a horizontal plane as the swinging assembly swings. The instrument is attached to a set of eyeglass that are worn on that person's head. A prism is suspended adjacent the eye. The pupil is viewed through the prism. The offset of the viewed image is measured and used to calculate the rear vertex distance.

    摘要翻译： 一种测量仪器及其相关的使用方法，用于记录人眼的瞳孔中心位置并确定与镜头的后顶点距离。 仪器具有底盘和可摆动地连接到底盘的自由摆动组件。 当摆动组件摆动时，摆动组件具有保持在水平平面中的对准点。 该仪器附着在佩戴在该人头上的一组眼镜上。 棱镜悬挂在眼睛附近。 瞳孔通过棱镜观察。 测量所观看图像的偏移并用于计算后顶点距离。

    Device and method for determining the height of the middle of the pupil in relation to the lowest part of a pair of eyeglasses
    9.
    发明授权
    Device and method for determining the height of the middle of the pupil in relation to the lowest part of a pair of eyeglasses 有权
    用于确定瞳孔中间相对于一副眼镜最低部分的高度的装置和方法

    公开(公告)号：US07540612B2

    公开(公告)日：2009-06-02

    申请号：US11210450

    申请日：2005-08-25

    申请人： Eric Fischer

    发明人： Eric Fischer

    IPC分类号： A61B3/10 ,  A61B3/14 ,  A61B3/04

    CPC分类号： A61B3/11 ,  G02C13/005

    摘要： A measurement instrument and its associated method of use to record a pupil center position of a person's eye. The instrument has a chassis and a free swinging assembly that is pivotably attached to the chassis. The swinging assembly has alignment points that remain in a horizontal plane as the swinging assembly swings. The instrument is attached to a set of eyeglass that are worn on that person's head. While wearing the measuring instrument, a person is made to assume a natural head position for a specific activity. Once a natural head position is found, the swinging assembly is set into a locked position. The pupil center point can then be determined by observing the now locked alignment points from a predetermined vantage point.

    摘要翻译： 一种测量仪器及其相关的用于记录人眼瞳孔中心位置的方法。 仪器具有底盘和可摆动地连接到底盘的自由摆动组件。 当摆动组件摆动时，摆动组件具有保持在水平平面中的对准点。 该仪器附着在佩戴在该人头上的一组眼镜上。 佩戴测量仪器时，人们会为了特定的活动而采取自然的头部位置。 一旦发现自然的头部位置，摆动组件被设置在锁定位置。 然后可以通过从预定的有利位置观察现在锁定的对准点来确定瞳孔中心点。

    Synthesis with automated placement information feedback
    10.
    发明授权
    Synthesis with automated placement information feedback 有权
    综合自动放置信息反馈

    公开(公告)号：US06701496B1

    公开(公告)日：2004-03-02

    申请号：US09620338

    申请日：2000-07-20

    申请人： Eric Fischer

    发明人： Eric Fischer

    IPC分类号： G06F1750

    CPC分类号： G06F17/5068 ,  G06F17/5045

    摘要： A method, system, and program product for designing and verifying an electronic circuit. A circuit logic design is translated into a netlist using a synthesis tool. The synthesis tool receives inputs of placing, routing, and timing information. Timing delays in the logic design are represented in the netlist using the placing and routing information. It is determined whether a timing goal has been reached based on the timing delays. When the timing goal has not been reached, changes are made to the placing, routing, and timing information, and the synthesis tool is re-executed using the changed information until the timing goal is reached.

    摘要翻译： 一种用于设计和验证电子电路的方法，系统和程序产品。 使用综合工具将电路逻辑设计转换为网表。 综合工具接收放置，路由和定时信息的输入。 使用放置和路由信息在网表中表示逻辑设计中的定时延迟。 基于定时延迟确定是否已经达到定时目标。 当没有达到定时目标时，对放置，路由和定时信息进行更改，并且使用改变的信息重新执行综合工具，直到达到时间目标。