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公开(公告)号:US08312309B2
公开(公告)日:2012-11-13
申请号:US12042985
申请日:2008-03-05
申请人: Eric L. Hendrickson , Sanjoy Mondal , Larry Thatcher , William Hodges , Lance Hacking , Sankaran Menon
发明人: Eric L. Hendrickson , Sanjoy Mondal , Larry Thatcher , William Hodges , Lance Hacking , Sankaran Menon
CPC分类号: G06F1/12
摘要: A technique to promote determinism among multiple clocking domains within a computer system or integrated circuit, In one embodiment, one or more execution units are placed in a deterministic state with respect to multiple clocks within a processor system having a number of different clocking domains.
摘要翻译: 一种用于促进计算机系统或集成电路内的多个时钟域之间的确定性的技术。在一个实施例中,一个或多个执行单元相对于具有多个不同计时域的处理器系统内的多个时钟被置于确定性状态。
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公开(公告)号:US20090228736A1
公开(公告)日:2009-09-10
申请号:US12042985
申请日:2008-03-05
申请人: Eric L. Hendrickson , Sanjoy Mondal , Larry Thatcher , William Hodges , Lance Hacking , Sankaran Menon
发明人: Eric L. Hendrickson , Sanjoy Mondal , Larry Thatcher , William Hodges , Lance Hacking , Sankaran Menon
IPC分类号: G06F1/04
CPC分类号: G06F1/12
摘要: A technique to promote determinism among multiple clocking domains within a computer system or integrated circuit, In one embodiment, one or more execution units are placed in a deterministic state with respect to multiple clocks within a processor system having a number of different clocking domains.
摘要翻译: 一种用于促进计算机系统或集成电路内的多个时钟域之间的确定性的技术。在一个实施例中,一个或多个执行单元相对于具有多个不同计时域的处理器系统内的多个时钟被置于确定性状态。
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公开(公告)号:US20070168767A1
公开(公告)日:2007-07-19
申请号:US11520203
申请日:2006-09-12
申请人: Talal Jaber , Srinivas Patil , Larry Thatcher , Chih-Jen Lin , Anil Sabbavarapu , David Wu , Madhukar Reddy
发明人: Talal Jaber , Srinivas Patil , Larry Thatcher , Chih-Jen Lin , Anil Sabbavarapu , David Wu , Madhukar Reddy
CPC分类号: G01R31/318552 , G01R31/318594 , G06F11/2236
摘要: A testing architecture for testing a complex integrated circuit in which each functional unit may be tested independently of the others. Embodiments of the invention allow testing of functional units to take place at slower or faster clock speeds than other portions of the processor without incurring delay or other adverse timing effects.
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