公开(公告)号：US20060075296A1

公开(公告)日：2006-04-06

申请号：US10956994

申请日：2004-09-30

Applicant: Sankaran Menon ,  Thomas Mozdzen

Inventor： Sankaran Menon ,  Thomas Mozdzen

IPC: G06F11/00

CPC classification number: G06F11/1012

Abstract: In some embodiments, a method, apparatus and system for data integrity of state retentive elements under low power modes are generally presented. In this regard, an integrity agent is introduced to generate one or more error checking bits for content within a logic block in response to an indication associated with a request to enter a low power mode. Other embodiments are also disclosed and claimed.

Abstract translation: 在一些实施例中，通常呈现用于在低功率模式下状态保持元件的数据完整性的方法，装置和系统。 在这方面，引入完整性代理以响应于与进入低功率模式的请求相关联的指示，为逻辑块内的内容生成一个或多个错误校验位。 还公开并要求保护其他实施例。

公开(公告)号：US20160018462A1

公开(公告)日：2016-01-21

申请号：US14335066

申请日：2014-07-18

Applicant: SANKARAN MENON ,  VASUDEV BIBIKAR ,  SAHAJANANDA REDDY P ,  SUNGHYUN KOH ,  NAVEENDRAN BALASINGAM

Inventor： SANKARAN MENON ,  VASUDEV BIBIKAR ,  SAHAJANANDA REDDY P ,  SUNGHYUN KOH ,  NAVEENDRAN BALASINGAM

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/31725 ,  G01R31/025 ,  G01R31/40 ,  G05F1/10

Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) having a reference input node; and a first multiplexer to provide a reference voltage to the reference input node and operable to select one of at least two different reference voltages as the reference voltage.

Abstract translation: 描述了一种装置，包括：具有参考输入节点的第一电压调节器（VR）; 以及第一多路复用器，用于向参考输入节点提供参考电压并且可操作以选择至少两个不同参考电压中的一个作为参考电压。

公开(公告)号：US20090228736A1

公开(公告)日：2009-09-10

申请号：US12042985

申请日：2008-03-05

Applicant: Eric L. Hendrickson ,  Sanjoy Mondal ,  Larry Thatcher ,  William Hodges ,  Lance Hacking ,  Sankaran Menon

Inventor： Eric L. Hendrickson ,  Sanjoy Mondal ,  Larry Thatcher ,  William Hodges ,  Lance Hacking ,  Sankaran Menon

IPC: G06F1/04

CPC classification number: G06F1/12

Abstract: A technique to promote determinism among multiple clocking domains within a computer system or integrated circuit, In one embodiment, one or more execution units are placed in a deterministic state with respect to multiple clocks within a processor system having a number of different clocking domains.

Abstract translation: 一种用于促进计算机系统或集成电路内的多个时钟域之间的确定性的技术。在一个实施例中，一个或多个执行单元相对于具有多个不同计时域的处理器系统内的多个时钟被置于确定性状态。

公开(公告)号：US20220018901A1

公开(公告)日：2022-01-20

申请号：US17377264

申请日：2021-07-15

Applicant: Keith A. Jones ,  Wai Mun Ng ,  Thomas A. Lyda ,  Subinlal Pk ,  Sankaran Menon ,  Vui Yong Liew ,  Kristan K. Wiseley

Inventor： Keith A. Jones ,  Wai Mun Ng ,  Thomas A. Lyda ,  Subinlal Pk ,  Sankaran Menon ,  Vui Yong Liew ,  Kristan K. Wiseley

IPC: G01R31/317 ,  G01R31/3185 ,  G01R31/3183

Abstract: An Automated Dynamic low voltage monitoring (LVM) based Low-Power (ADLLP) debug capability for a system-on-chip (SoC) as well as the open/closed-chassis platform for faster TTM (Time to Market) of the final platform or system. ADLLP Debug is achieved by detection of the probe connection between a target system (e.g., SoC) and debug host system. A user can dynamically override the power, clocks and LVM for intellectual property (IP) blocks not part of the debug trace by instructing a Power Management Controller (PMC) via the Inter Processor Communication (IPC) mailbox (or any other suitable mailbox driver) to set the registers in a Target Firmware (TFW) based on the probe and debug use-case.

公开(公告)号：US08312309B2

公开(公告)日：2012-11-13

申请号：US12042985

申请日：2008-03-05

Applicant: Eric L. Hendrickson ,  Sanjoy Mondal ,  Larry Thatcher ,  William Hodges ,  Lance Hacking ,  Sankaran Menon

Inventor： Eric L. Hendrickson ,  Sanjoy Mondal ,  Larry Thatcher ,  William Hodges ,  Lance Hacking ,  Sankaran Menon

IPC: G06F1/12 ,  G06F11/00

CPC classification number: G06F1/12

Abstract: A technique to promote determinism among multiple clocking domains within a computer system or integrated circuit, In one embodiment, one or more execution units are placed in a deterministic state with respect to multiple clocks within a processor system having a number of different clocking domains.

Abstract translation: 一种用于促进计算机系统或集成电路内的多个时钟域之间的确定性的技术。在一个实施例中，一个或多个执行单元相对于具有多个不同计时域的处理器系统内的多个时钟被置于确定性状态。

公开(公告)号：US20150186232A1

公开(公告)日：2015-07-02

申请号：US14141099

申请日：2013-12-26

Applicant: Jeremy Conner ,  Sabar Souag ,  Karunakara Kotary ,  Victor Ruybalid ,  Noel Eck ,  Ramana Rachakonda ,  Sankaran Menon ,  Lance Hacking

Inventor： Jeremy Conner ,  Sabar Souag ,  Karunakara Kotary ,  Victor Ruybalid ,  Noel Eck ,  Ramana Rachakonda ,  Sankaran Menon ,  Lance Hacking

IPC: G06F11/22 ,  G06F11/26

CPC classification number: G06F11/2268 ,  G06F11/26 ,  G06F11/3024 ,  G06F11/3082 ,  G06F11/3086 ,  G06F11/3476 ,  G06F11/3656 ,  G06F2201/835 ,  G06F2201/865

Abstract: Techniques of debugging a computing system are described herein. The techniques may include generating debug data at agents in the computing system. The techniques may include recording the debug data at a storage element, wherein the storage element is disposed in a non-core portion of the circuit interconnect accessible to the agents.

Abstract translation: 这里描述了调试计算系统的技术。 这些技术可以包括在计算系统中的代理处生成调试数据。 这些技术可以包括将调试数据记录在存储元件处，其中存储元件设置在代理可访问的电路互连的非核心部分中。

公开(公告)号：US20080104466A1

公开(公告)日：2008-05-01

申请号：US11963689

申请日：2007-12-21

Applicant: Sankaran Menon ,  Luis Basto ,  Tien Dinh ,  Thomas Tomazin ,  Juan Revilla

Inventor： Sankaran Menon ,  Luis Basto ,  Tien Dinh ,  Thomas Tomazin ,  Juan Revilla

IPC: G01R31/28

CPC classification number: G11C29/48 ,  G01R31/318508 ,  G01R31/318513 ,  G01R31/318541 ,  G01R31/318555 ,  G11C2029/0401 ,  G11C2029/3202

Abstract: The inputs to an embedded core, e.g., the core terminals, may not be directly connected to pins on the SoC. The lack of direct access to an embedded core's terminals may complicate testing of the embedded core. A test wrapper including boundary scan test (BST) cells may be used to test an embedded core. Dual function BST/ATPG (Automatic Test Pattern Generation) cells may be used to perform both BST and ATPG tests on embedded cores. A BIST (Built-In Self Test) controller supporting a “resume” mode in addition to a “pass/fail” mode may be used to compensate for timing latencies introduced by pipeline staging in an embedded memory array.

Abstract translation: 嵌入式核心（例如核心终端）的输入可能不直接连接到SoC上的引脚。 直接访问嵌入式核心终端的可能会使嵌入式核心的测试复杂化。 可以使用包括边界扫描测试（BST）单元的测试包装器来测试嵌入式核心。 双功能BST / ATPG（自动测试模式生成）单元可用于对嵌入式核心执行BST和ATPG测试。 可以使用支持“通过/失败”模式的“恢复”模式的BIST（内置自测）控制器来补偿由嵌入式存储器阵列中的流水线分级引入的定时延迟。

公开(公告)号：US20070136564A1

公开(公告)日：2007-06-14

申请号：US11302742

申请日：2005-12-14

Applicant: Sankaran Menon ,  John Fernando ,  Ravi Kolagotla

Inventor： Sankaran Menon ,  John Fernando ,  Ravi Kolagotla

IPC: G06F9/44

CPC classification number: G11C29/32 ,  G11C2029/3202

Abstract: Apparatus including a save path to connect an output of a first latch of a first save/restore cell of a save/restore chain to an input of a second latch of the first save/restore cell, a restore path to connect an output from the second latch to an input of the first latch, and a scan path to connect the output of the second latch to an input of a second save/restore cell of the save/restore chain. The apparatus is useful for fast context switching.

Abstract translation: 一种装置，包括将保存/恢复链的第一保存/恢复单元的第一锁存器的输出连接到第一存储/恢复单元的第二锁存器的输入的保存路径，连接来自第一存储/恢复单元的输出的恢复路径 第二锁存器到第一锁存器的输入端，以及扫描路径，用于将第二锁存器的输出连接到保存/恢复链路的第二保存/恢复单元的输入。 该装置对于快速上下文切换是有用的。