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1.发明授权Digital communications modulator having a modulation processor which supports high data rates 失效具有支持高数据速率的调制处理器的数字通信调制器公开(公告)号：US06337606B1
公开(公告)日：2002-01-08
申请号：US09241697
申请日：1999-02-02
IPC分类号： H04L2720
CPC分类号： H04L25/03834 , H04L27/2071
摘要： An IC modulation processor (28) may be configured to operate in a single chip mode to accommodate baud rates up to a maximum clock rate for the processor (28) and in a dual chip mode to accommodate baud rates in excess of the maximum clock rate. The IC modulation processor (28) performs digital processing on a communication signal which conveys an input data stream (22). A pulse shaping filter (54-57) is provided following a phase mapper (50). The pulse shaping filter (54-57) is implemented as a pair of half-filters. Pulse shaping is distributed between two IC modulation processors (28) in the dual chip mode. An interpolator (86) and linearizer (106) follow the pulse shaping filters (54-57).
摘要翻译： IC调制处理器（28）可以被配置为以单芯片模式操作以适应处理器（28）的最大时钟速率的波特率，并且以双芯片模式适应超过最大时钟速率的波特率 。 IC调制处理器（28）对传送输入数据流（22）的通信信号执行数字处理。 在相位映射器（50）之后提供脉冲整形滤波器（54-57）。 脉冲整形滤波器（54-57）被实现为一对半滤波器。 在双芯片模式下，脉冲整形分布在两个IC调制处理器（28）之间。 内插器（86）和线性化器（106）跟随脉冲整形滤波器（54-57）。
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2.发明授权Digital communications modulator having an interpolator upstream of a linearizer and method therefor 失效具有线性化器上游的内插器的数字通信调制器及其方法公开(公告)号：US06362701B1
公开(公告)日：2002-03-26
申请号：US09709885
申请日：2000-11-09
IPC分类号： H04L2720
CPC分类号： H04L25/03834 , H04L27/2071
摘要： An IC modulation processor (28) may be configured to operate in a single chip mode to accommodate baud rates up to a maximum clock rate for the processor (28) and in a dual chip mode to accommodate baud rates in excess of the maximum clock rate. The IC modulation processor (28) performs digital processing on a communication signal which conveys an input data stream (22). A pulse shaping filter (54-57) is provided following a phase mapper (50). The pulse shaping filter (54-57) is implemented as a pair of half-filters. Pulse shaping is distributed between two IC modulation processors (28) in the dual chip mode. An interpolator (86) and linearizer (106) follow the pulse shaping filters (54-57).
摘要翻译： IC调制处理器（28）可以被配置为以单芯片模式操作以适应处理器（28）的最大时钟速率的波特率，并且以双芯片模式适应超过最大时钟速率的波特率 。 IC调制处理器（28）对传送输入数据流（22）的通信信号执行数字处理。 在相位映射器（50）之后提供脉冲整形滤波器（54-57）。 脉冲整形滤波器（54-57）被实现为一对半滤波器。 在双芯片模式下，脉冲整形分布在两个IC调制处理器（28）之间。 内插器（86）和线性化器（106）跟随脉冲整形滤波器（54-57）。
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公开(公告)号：US06735734B1
公开(公告)日：2004-05-11
申请号：US09561222
申请日：2000-04-28
IPC分类号： H04J322
CPC分类号： H04L1/0059 , H04L1/0041 , H04L1/0045 , H04L1/0065 , H04L1/0071 , H04L1/0083 , H04L2001/0093 , H04L2001/0098
摘要： A TDM data distribution system (10) includes a hub unit (12) with a multipoint transmitter (24) and any number of subscriber units (14), each of which has a multipoint receiver (28). A forward communication link (16) transmitted by the hub unit (12) exhibits a substantially constant baud and carrier frequency over a number of diverse modulation format (MF) time slots (42). However, the different MF slots (42) convey data using different modulation formats. Modulation order and coding rate may vary for different modulation formats. The multipoint transmitter (24) includes a number of encoding FEC processors (48), wherein each encoding FEC processor (48) is active only for selected ones of the different MF slots (42). When inactive, the internal states of the encoding FEC processors (48) are frozen. Each multipoint receiver (28) includes a decoding FEC processor (108) which is active only for MF slots (42) assigned to the same modulation format for which the decoding FEC processors (108) are programmed. When inactive, the internal states of the decoding FEC processors (108) are frozen.
摘要翻译： TDM数据分发系统（10）包括具有多点发射机（24）和任意数目的用户单元（14）的集线器单元（12），每个用户单元（14）具有多点接收机（28）。 由集线器单元（12）发送的前向通信链路（16）在多个不同调制格式（MF）时隙（42）上呈现基本恒定的波特率和载波频率。 然而，不同的MF时隙（42）使用不同的调制格式传送数据。 对于不同的调制格式，调制顺序和编码率可能会有所不同。 多点发射机（24）包括多个编码FEC处理器（48），其中每个编码FEC处理器（48）仅对不同MF时隙（42）中的选定的一个处理器有效。 当不活动时，编码FEC处理器（48）的内部状态被冻结。 每个多点接收器（28）包括解码FEC处理器（108），其仅对分配给解码FEC处理器（108）编程的相同调制格式的MF时隙（42）有效。 当不活动时，解码FEC处理器（108）的内部状态被冻结。
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4.发明授权
公开(公告)号：US5774084A
公开(公告)日：1998-06-30
申请号：US627930
申请日：1996-04-03
摘要： A pulse width modulation (PWM) circuit translates digital data into an analog signal. The PWM circuit includes at least a digital counter, a significance reverser, and a comparator circuit. The significance reverser reverses the relative order of significance of at least two bits in the count words generated by the counter. The comparator determines whether the magnitude of a digital input word is greater than the magnitude of the reversed order count word. The PWM circuit produces a high output when the magnitude of the input word is greater than the magnitude of the reversed order count word and a low output when the magnitude of the input word is not greater than the magnitude of the reversed order count word. The analog output produced by the PWM circuit includes a number of pulses evenly distributed during the count cycle of the counter, and the input word indicates a duty cycle for the analog output. The PWM circuit includes a programmable output gain feature and an output interface that mimics the output configuration of conventional phase/frequency detector circuits.
摘要翻译： 脉冲宽度调制（PWM）电路将数字数据转换为模拟信号。 PWM电路至少包括一个数字计数器，一个有效反向器和一个比较器电路。 显着性反转器反转由计数器产生的计数字中至少两位的显着性的相对顺序。 比较器确定数字输入字的大小是否大于反转顺序计数字的大小。 当输入字的大小大于反相计数字的大小时，PWM电路产生高输出，而当输入字的大小不大于反转顺序计数字的大小时，PWM电路产生高输出。 由PWM电路产生的模拟输出包括在计数器的计数周期期间均匀分布的脉冲数，输入字表示模拟输出的占空比。 PWM电路包括可编程输出增益特征和模拟常规相位/频率检测器电路的输出配置的输出接口。
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公开(公告)号：US5949832A
公开(公告)日：1999-09-07
申请号：US820084
申请日：1997-03-19
CPC分类号： H04L1/0059 , H04L1/0001 , H04L1/0054 , H04L1/203
摘要： A digital data receiver includes a tunable analog matched filter circuit having a variable bandwidth responsive to the bit error rate (BER) of the decoded data. The bandwidth of the analog filtering circuit is controlled by a tuning control signal that includes a coarse tuning signal combined with a fine tuning signal. The coarse tuning signal is generated by a frequency-to-current converter and the fine tuning signal is generated by a current-scaling digital-to-analog converter (DAC). The DAC input signal is produced by a DAC control circuit that includes a BER comparator and a DAC control state machine. The BER comparator determines whether the BER has improved or degraded in response to a previous tuning command. To optimize the BER in the decoded data signal, the state machine increments or decrements the value of the fine tuning signal, which in turn alters the filter bandwidth.
摘要翻译： 数字数据接收机包括具有响应于解码数据的误码率（BER）的可变带宽的可调谐模拟匹配滤波器电路。 模拟滤波电路的带宽由包括与微调信号组合的粗调谐信号的调谐控制信号控制。 粗调谐信号由频率 - 电流转换器产生，微调信号由电流比例数模转换器（DAC）产生。 DAC输入信号由包括BER比较器和DAC控制状态机的DAC控制电路产生。 BER比较器确定BER是否响应于先前的调谐命令而改善或降级。 为了优化解码数据信号中的BER，状态机递增或递减微调信号的值，从而改变滤波器带宽。
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公开(公告)号：US5721756A
公开(公告)日：1998-02-24
申请号：US620671
申请日：1996-03-26
摘要： A digital data receiver includes tunable analog components having variable parameters that are responsive to the bit error rate (BER) of the decoded digital data. The analog components include a quadrature generator having a tunable phase shifter, an analog filter having a tunable bandwidth, a tunable magnitude equalizer circuit, a tunable group delay equalizer circuit, and an amplifier having an adjustable gain. The tunable components are controlled by tuning control signals that incorporate digitally-produced fine tuning signals. The digital tuning signals are altered in accordance with realtime changes in the BER.
摘要翻译： 数字数据接收机包括具有可变参数的可调模拟分量，该参数响应于解码的数字数据的误码率（BER）。 模拟部件包括具有可调谐移相器的正交发生器，具有可调谐带宽的模拟滤波器，可调幅度均衡器电路，可调组延迟均衡器电路和具有可调节增益的放大器。 通过调谐控制信号控制可调组件，该控制信号包含数字产生的微调信号。 数字调谐信号根据BER的实时变化而改变。
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