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    System and Method of Processing Hierarchical Very Long Instruction Packets
    3.
    发明申请
    System and Method of Processing Hierarchical Very Long Instruction Packets 有权
    处理分层超长指令包的系统和方法

    公开(公告)号：US20110219212A1

    公开(公告)日：2011-09-08

    申请号：US12716359

    申请日：2010-03-03

    申请人： Lucian Codrescu ,  Erich James Plondke ,  Ajay Anant Ingle ,  Suresh K. Venkumahanti ,  Charles Joseph Tabony

    发明人： Lucian Codrescu ,  Erich James Plondke ,  Ajay Anant Ingle ,  Suresh K. Venkumahanti ,  Charles Joseph Tabony

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3853 ,  G06F9/30149

    摘要： A system and method of processing a hierarchical very long instruction word (VLIW) packet is disclosed. In a particular embodiment, a method of processing instructions is disclosed. The method includes receiving a hierarchical VLIW packet of instructions and decoding an instruction from the packet to determine whether the instruction is a single instruction or whether the instruction includes a subpacket that includes a plurality of sub-instructions. The method also includes, in response to determining that the instruction includes the subpacket, executing each of the sub-instructions.

    摘要翻译： 公开了一种处理分级非常长的指令字（VLIW）分组的系统和方法。 在特定实施例中，公开了一种处理指令的方法。 该方法包括：接收分层VLIW指令分组，并对来自分组的指令进行解码，以确定该指令是单个指令还是指令是否包括包含多个子指令的子分组。 响应于确定该指令包括子分组，该方法还包括执行每个子指令。

    Bimodal Compare Predictor Encoded In Each Compare Instruction
    7.
    发明申请
    Bimodal Compare Predictor Encoded In Each Compare Instruction 审中-公开
    在每个比较指令中编码的双模比较预测器

    公开(公告)号：US20130283023A1

    公开(公告)日：2013-10-24

    申请号：US13449754

    申请日：2012-04-18

    申请人： Charles Joseph Tabony ,  Lucian Codrescu ,  Suresh K. Venkumahanti

    发明人： Charles Joseph Tabony ,  Lucian Codrescu ,  Suresh K. Venkumahanti

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30021 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/3832

    摘要： Systems and methods for branch prediction, including predicting evaluation of a producer instruction such as a compare instruction, by encoding a prediction field in the producer instruction, and predicting evaluation of the producer instruction by using the encoded prediction field. A consumer instruction such as a conditional branch instruction predicated on the producer instruction can be speculatively executed based on the predicted evaluation of the producer instruction. The producer instruction is executed in an execution pipeline to determine an actual evaluation of the producer instruction, and the prediction field is updated, if necessary, based on the actual evaluation and the predicted evaluation. The producer instruction can be updated in memory with the updated prediction field.

    摘要翻译： 用于分支预测的系统和方法，包括通过编码生成器指令中的预测字段来预测诸如比较指令的生成器指令的评估，以及通过使用编码的预测字段来预测生成器指令的评估。 可以基于生成器指令的预测评估，推测性地执行诸如基于生成器指令的条件分支指令的消费者指令。 生产者指令在执行管线中执行以确定生产者指令的实际评估，并且如果需要，基于实际评估和预测评估来更新预测字段。 生成器指令可以在更新的预测字段的存储器中更新。

    Methods and Apparatus for Constant Extension in a Processor
    9.
    发明申请
    Methods and Apparatus for Constant Extension in a Processor 审中-公开
    处理器中恒定扩展的方法和装置

    公开(公告)号：US20120284489A1

    公开(公告)日：2012-11-08

    申请号：US13155565

    申请日：2011-06-08

    申请人： Erich James Plondke ,  Lucian Codrescu ,  Charles Joseph Tabony ,  Suresh K. Venkumahanti ,  Ajay Anant Ingle

    发明人： Erich James Plondke ,  Lucian Codrescu ,  Charles Joseph Tabony ,  Suresh K. Venkumahanti ,  Ajay Anant Ingle

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30192 ,  G06F9/30167

    摘要： Programs often require constants that cannot be encoded in a native instruction format, such as 32-bits. To provide an extended constant, an instruction packet is formed with constant extender information and a target instruction. The constant extender information encoded as a constant extender instruction provides a first set of constant bits, such as 26-bits for example, and the target instruction provides a second set of constant bits, such as 6-bits. The first set of constant bits are combined with the second set of constant bits to generate an extended constant for execution of the target instruction. The extended constant may be used as an extended source operand, an extended address for memory access instructions, an extended address for branch type of instructions, and the like. Multiple constant extender instructions may be used together to provide larger constants than can be provided by a single extension instruction.

    摘要翻译： 程序通常需要不能以本机指令格式编码的常量，例如32位。 为了提供扩展常数，形成具有恒定扩展器信息和目标指令的指令包。 编码为恒定扩展器指令的恒定扩展器信息提供第一组常量位，例如26位，目标指令提供第二组常数位，例如6位。 第一组常数位与第二组常数位组合以产生用于执行目标指令的扩展常数。 扩展常数可以用作扩展源操作数，存储器访问指令的扩展地址，分支类型的指令的扩展地址等。 多个恒定扩展器指令可以一起使用以提供比单个扩展指令可以提供的更大的常数。