公开(公告)号：US20140082421A1

公开(公告)日：2014-03-20

申请号：US13619248

申请日：2012-09-14

申请人： Erik Jan Marinissen ,  Sergej Deutsch

发明人： Erik Jan Marinissen ,  Sergej Deutsch

IPC分类号： G06F11/263

CPC分类号： G01R31/318575 ,  G01R31/31721 ,  G01R31/318552

摘要： A method is provided to test a modular integrated circuit (IC) comprising: testing a module-under-test (MUT) within the IC while causing a controlled toggle rate within a first neighbor module of the MUT; wherein the controlled toggle rate within the first neighbor module is selected so that toggling within the first neighbor module has substantially the same effect upon operation of the MUT that operation of the first neighbor module would have during actual normal functional operation of the first neighbor module.

摘要翻译： 提供了一种用于测试模块化集成电路（IC）的方法，包括：测试IC内的模块测试（MUT），同时在MUT的第一相邻模块内引起受控的切换速率; 其中，选择所述第一相邻模块内的受控切换速率，使得在所述第一相邻模块中的切换对于所述第一相邻模块的实际正常功能操作期间将具有的所述MUT的操作具有基本相同的效果。

公开(公告)号：US08914689B2

公开(公告)日：2014-12-16

申请号：US13619248

申请日：2012-09-14

申请人： Erik Jan Marinissen ,  Sergej Deutsch

发明人： Erik Jan Marinissen ,  Sergej Deutsch

IPC分类号： G01R31/28

CPC分类号： G01R31/318575 ,  G01R31/31721 ,  G01R31/318552

摘要： A method is provided to test a modular integrated circuit (IC) comprising: testing a module-under-test (MUT) within the IC while causing a controlled toggle rate within a first neighbor module of the MUT; wherein the controlled toggle rate within the first neighbor module is selected so that toggling within the first neighbor module has substantially the same effect upon operation of the MUT that operation of the first neighbor module would have during actual normal functional operation of the first neighbor module.

摘要翻译： 提供了一种用于测试模块化集成电路（IC）的方法，包括：测试IC内的模块测试（MUT），同时在MUT的第一相邻模块内引起受控的切换速率; 其中，选择所述第一相邻模块内的受控切换速率，使得在所述第一相邻模块中的切换对于所述第一相邻模块的实际正常功能操作期间将具有的所述MUT的操作具有基本相同的效果。

公开(公告)号：US20190229925A1

公开(公告)日：2019-07-25

申请号：US16369989

申请日：2019-03-29

申请人： Michael Kounavis ,  Sergej Deutsch ,  David M. Durham ,  Karanvir Grewal

发明人： Michael Kounavis ,  Sergej Deutsch ,  David M. Durham ,  Karanvir Grewal

IPC分类号： H04L9/32 ,  H04L9/06 ,  G06F11/20

摘要： The present disclosure is directed to systems and methods for the secure transmission of plaintext data blocks encrypted using a NIST standard encryption to provide a plurality of ciphertext data blocks, and using the ciphertext data blocks to generate a Galois multiplication-based authentication tag and parity information that is communicated in parallel with the ciphertext blocks and provides a mechanism for error detection, location and correction for a single ciphertext data block or a plurality of ciphertext data blocks included on a storage device. The systems and methods include encrypting a plurality of plaintext blocks to provide a plurality of ciphertext blocks. The systems and methods include generating a Galois Message Authentication Code (GMAC) authentication tag and parity information using the ciphertext blocks. The GMAC authentication tag may be encrypted to provide a GIMAC authentication tag that is communicated in parallel with the ciphertext blocks to one or more recipient systems or devices.

公开(公告)号：US20170285976A1

公开(公告)日：2017-10-05

申请号：US15089140

申请日：2016-04-01

申请人： David M. Durham ,  Siddhartha Chhabra ,  Michael E. Kounavis ,  Sergej Deutsch ,  Karanvir S. Grewal ,  Joseph F. Cihula ,  Saeedeh Komijani

发明人： David M. Durham ,  Siddhartha Chhabra ,  Michael E. Kounavis ,  Sergej Deutsch ,  Karanvir S. Grewal ,  Joseph F. Cihula ,  Saeedeh Komijani

IPC分类号： G06F3/06 ,  G06F12/08 ,  G06F12/14

CPC分类号： G06F12/1408 ,  G06F21/64 ,  G06F21/79 ,  G06F2212/60

摘要： Apparatus, systems, computer readable storage mediums and/or methods may provide memory integrity by using unused physical address bits (or other metadata passed through cache) to manipulate cryptographic memory integrity values, allowing software memory allocation routines to control the assignment of pointers (e.g., implement one or more access control policies). Unused address bits (e.g., because of insufficient external memory) passed through cache, may encode key domain information in the address so that different key domain addresses alias to the same physical memory location. Accordingly, by mixing virtual memory mappings and cache line granularity aliasing, any page in memory may contain a different set of aliases at the cache line level and be non-deterministic to an adversary.

公开(公告)号：US20180091308A1

公开(公告)日：2018-03-29

申请号：US15816901

申请日：2017-11-17

申请人： David M. Durham ,  Rajat Agarwal ,  Siddhartha Chhabra ,  Sergej Deutsch ,  Karanvir S. Grewal ,  Ioannis T. Schoinas

发明人： David M. Durham ,  Rajat Agarwal ,  Siddhartha Chhabra ,  Sergej Deutsch ,  Karanvir S. Grewal ,  Ioannis T. Schoinas

IPC分类号： H04L9/32 ,  G06F3/06 ,  H04L9/06 ,  G06F11/10 ,  G11C29/52

摘要： In one example, a system for managing encrypted memory comprises a processor to store a first MAC based on data stored in system memory in response to a write operation to the system memory. The processor can also detect a read operation corresponding to the data stored in the system memory, calculate a second MAC based on the data retrieved from the system memory, determine that the second MAC does not match the first MAC, and recalculate the second MAC with a correction operation, wherein the correction operation comprises an XOR operation based on the data retrieved from the system memory and a replacement value for a device of the system memory. Furthermore, the processor can decrypt the data stored in the system memory in response to detecting the recalculated second MAC matches the first MAC and transmit the decrypted data to cache thereby correcting memory errors.