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公开(公告)号：US06859873B2
公开(公告)日：2005-02-22
申请号：US09878145
申请日：2001-06-08
CPC分类号： G06F9/3824 , G06F9/3867
摘要： A variable length instruction pipeline includes optional expansion stages that can be included in the variable length instruction pipeline to avoid pipeline stalls. The expansion stages are removed from the variable length instruction pipeline when not needed to reduce the length of the pipeline, which reduces latency and other problems associated with long pipelines. For example, in one embodiment of the present invention, a variable length instruction pipeline includes a first pipeline stage, a first expansion stage, and a second pipeline stage. The second pipeline stage is configured to selectively receive instructions from the first pipeline stage or the first expansion stage if the first expansion stage holds an instruction.
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公开(公告)号：US07260707B2
公开(公告)日：2007-08-21
申请号：US11053096
申请日：2005-02-07
IPC分类号： G06F9/38
CPC分类号： G06F9/3824 , G06F9/3867
摘要： A variable length instruction pipeline includes optional expansion stages that can be included in the variable length instruction pipeline to avoid pipeline stalls. The expansion stages are removed from the variable length instruction pipeline when not needed to reduce the length of the pipeline, which reduces latency and other problems associated with long pipelines. For example, in one embodiment of the present invention, a variable length instruction pipeline includes a first pipeline stage, a first expansion stage, and a second pipeline stage. The second pipeline stage is configured to selectively receive instructions from the first pipeline stage or the first expansion stage if the first expansion stage holds an instruction.
摘要翻译： 可变长度指令流水线包括可以包括在可变长度指令流水线中以避免流水线停顿的可选扩展阶段。 当不需要缩短管道长度时，从可变长度指令流水线中移除扩展级，这减少了与长流水线相关联的延迟和其他问题。 例如，在本发明的一个实施例中，可变长度指令流水线包括第一流水线阶段，第一扩展阶段和第二流水线阶段。 第二流水线级被配置为如果第一扩展级保持指令，则选择性地接收来自第一流水线级或第一扩展级的指令。
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3.发明授权Interrupt and trap handling in an embedded multi-thread processor to avoid priority inversion and maintain real-time operation 有权嵌入式多线程处理器中的中断和陷阱处理，以避免优先级倒置并保持实时操作公开(公告)号：US07774585B2
公开(公告)日：2010-08-10
申请号：US10712473
申请日：2003-11-12
IPC分类号： G06F9/00
CPC分类号： G06F9/4812 , G06F9/462 , G06F13/26
摘要： A real-time, multi-threaded embedded system includes rules for handling traps and interrupts to avoid problems such as priority inversion and re-entrancy. By defining a global interrupt priority value for all active threads and only accepting interrupts having a priority higher than the interrupt priority value, priority inversion can be avoided. Switching to the same thread before any interrupt servicing, and disabling interrupts and thread switching during interrupt servicing can simplify the interrupt handling logic. By storing trap background data for traps and servicing traps only in their originating threads, trap traceability can be preserved. By disabling interrupts and thread switching during trap servicing, unintended trap re-entrancy and servicing disruption can be prevented.
摘要翻译： 一个实时的多线程嵌入式系统包括处理陷阱和中断的规则，以避免诸如优先级倒置和重入的问题。 通过为所有活动线程定义全局中断优先级值，并且仅接受优先级高于中断优先级值的中断，可以避免优先级反转。 在任何中断服务之前切换到同一个线程，并且在中断服务期间禁用中断和线程切换可以简化中断处理逻辑。 通过仅在其始发线程中存储陷阱和维护陷阱的陷阱后台数据，可以保留陷阱跟踪性。 通过在陷阱维护期间禁用中断和线程切换，可以防止意外的陷阱重入和服务中断。
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公开(公告)号：US07263599B2
公开(公告)日：2007-08-28
申请号：US10774226
申请日：2004-02-06
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/3808
摘要： A multithreaded processor includes a thread ID for each set of fetched bits in an instruction fetch and issue unit. The thread ID attaches to the instructions and operands of the set of fetched bits. Pipeline stages in the multithreaded processor stores the thread ID associated with each operand or instruction in the pipeline stage. The thread ID are used to maintain data coherency and to generate program traces that include thread information for the instructions executed by the multithreaded processor.
摘要翻译： 多线程处理器包括在指令获取和发布单元中的每组提取位的线程ID。 线程ID附加到获取位集合的指令和操作数。 多线程处理器中的管道级存储与流水线级中的每个操作数或指令相关联的线程ID。 线程ID用于维护数据一致性并生成包含由多线程处理器执行的指令的线程信息的程序跟踪。
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5.发明授权Multi-threaded embedded processor using deterministic instruction memory to guarantee execution of pre-selected threads during blocking events 有权多线程嵌入式处理器使用确定性指令存储器来保证在阻塞事件期间预先选择的线程的执行公开(公告)号：US07062606B2
公开(公告)日：2006-06-13
申请号：US10431996
申请日：2003-05-07
申请人： Robert E. Ober , Roger D. Arnold , Daniel Martin , Erik K. Norden
发明人： Robert E. Ober , Roger D. Arnold , Daniel Martin , Erik K. Norden
IPC分类号： G06F12/00
CPC分类号： G06F9/3802 , G06F9/3851 , G06F12/126 , G06F2212/2515 , Y02D10/13
摘要： A multi-threaded embedded processor that includes an on-chip deterministic (e.g., scratch or locked cache) memory that persistently stores all instructions associated with one or more pre-selected high-use threads. The processor executes general (non-selected) threads by reading instructions from an inexpensive external memory, e.g., by way of an on-chip standard cache memory, or using other potentially slow, non-deterministic operation such as direct execution from that external memory that can cause the processor to stall while waiting for instructions to arrive. When a cache miss or other blocking event occurs during execution of a general thread, the processor switches to the pre-selected thread, whose execution with zero or minimal delay is guaranteed by the deterministic memory, thereby utilizing otherwise wasted processor cycles until the blocking event is complete.
摘要翻译： 一种多线程嵌入式处理器，其包括持续存储与一个或多个预选高使用线程相关联的所有指令的片上确定性（例如，划伤或锁定的高速缓存）存储器。 处理器通过从便宜的外部存储器读取指令（例如，通过片上标准高速缓冲存储器）或使用其他潜在的慢速非确定性操作（例如来自该外部存储器的直接执行）来执行通用（未选择）线程 这可能导致处理器在等待指令到达时停止。 当在一般线程的执行期间出现高速缓存未命中或其他阻塞事件时，处理器切换到预先选择的线程，该线程的执行以零或最小延迟由确定性存储器保证，从而利用其他浪费的处理器周期，直到阻塞事件 做完了。
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公开(公告)号：US07360203B2
公开(公告)日：2008-04-15
申请号：US10774193
申请日：2004-02-06
IPC分类号： G06F9/45
CPC分类号： G06F9/3851 , G06F9/3824 , G06F9/3826 , G06F9/3861
摘要： A multithreaded processor includes a thread ID for each set of fetched bits in an instruction fetch and issue unit. The thread ID attaches to the instructions and operands of the set of fetched bits. Pipeline stages in the multithreaded processor stores the thread ID associated with each operand or instruction in the pipeline stage. The thread ID are used to maintain data coherency and to generate program traces that include thread information for the instructions executed by the multithreaded processor.
摘要翻译： 多线程处理器包括在指令获取和发布单元中的每组提取位的线程ID。 线程ID附加到获取位集合的指令和操作数。 多线程处理器中的管道级存储与流水线级中的每个操作数或指令相关联的线程ID。 线程ID用于维护数据一致性并生成包含由多线程处理器执行的指令的线程信息的程序跟踪。
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公开(公告)号：US06378065B1
公开(公告)日：2002-04-23
申请号：US09069030
申请日：1998-04-27
申请人： Roger D. Arnold , Alfred Eder
发明人： Roger D. Arnold , Alfred Eder
IPC分类号： G06F900
CPC分类号： G06F9/30141 , G06F9/30116 , G06F9/30123 , G06F9/462 , G11C7/00
摘要： The present invention relates to a data processing unit, comprising at least one register having at least one read port and one write port. The register has at least two memory cells each having a write line and a read line, a first switch having inputs and one output for coupling said read line of one of said memory cells with said read port, second switch for coupling said write line of one of said memory cells with said write port.
摘要翻译： 本发明涉及一种数据处理单元，包括至少一个具有至少一个读端口和一个写端口的寄存器。 寄存器具有至少两个具有写入线和读取线的存储器单元，具有输入的第一开关和用于将所述存储器单元之一的所述读取线与所述读取端口耦合的第一开关，用于将所述写入线 所述存储单元中的一个具有所述写入端口。
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8.发明授权Data processing unit with debug capabilities using a memory protection unit 失效具有使用存储器保护单元的调试功能的数据处理单元公开(公告)号：US06175913B1
公开(公告)日：2001-01-16
申请号：US08928768
申请日：1997-09-12
申请人： Eric Chesters , Roger D. Arnold , Rod G. Fleck
发明人： Eric Chesters , Roger D. Arnold , Rod G. Fleck
IPC分类号： G06F1500
CPC分类号： G06F11/3636 , G06F11/3656
摘要： A data processing unit is described which comprises a central processing unit, a bus coupled with the central processing unit to access a device via address and data lines coupled with the bus. A debug unit is coupled to the bus, a protection unit is coupled with the bus and with the debug unit for protecting access on the bus. The protection unit is programmable to operate in a protecting mode in which the bus can be protected and in a debug mode in which a signal is sent to the debug unit, whereupon the debug unit generates a debug signal.
摘要翻译： 描述了一种数据处理单元，其包括中央处理单元，与中央处理单元耦合的总线，以经由与总线耦合的地址和数据线访问设备。 调试单元耦合到总线，保护单元与总线和调试单元耦合，用于保护总线上的访问。 保护单元可编程为在保护模式下工作，其中总线可以被保护，并且在调制模式中，信号被发送到调试单元，于是调试单元产生调试信号。
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9.发明授权Fixed length memory to memory arithmetic and architecture for a communications embedded processor system 有权用于通信嵌入式处理器系统的固定长度存储器到存储器算术和架构公开(公告)号：US07047396B1
公开(公告)日：2006-05-16
申请号：US09888295
申请日：2001-06-22
IPC分类号： G06F7/38
CPC分类号： G06F9/3016 , G06F7/49994 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30167 , G06F9/30192 , G06F9/34 , G06F9/3812
摘要： A method and system for fixed-length memory-to-memory processing of fixed-length instructions. Further, the present invention is a method and system for implementing a memory operand width independent of the ALU width. The arithmetic and register data are 32 bits, but the memory operand is variable in size. The size of the memory operand is specified by the instruction. Instructions in accordance with the present invention allow for multiple memory operands in a single fixed-length instruction. The instruction set is small and simple, so the implementation is lower cost than traditional processors. More addressing modes are provided for, thus creating a more efficient code. Semaphores are implemented using a single bit. Shift-and-merge instructions are used to access data across word boundaries.
摘要翻译： 一种固定长度存储器到存储器处理固定长度指令的方法和系统。 此外，本发明是用于实现与ALU宽度无关的存储器操作数宽度的方法和系统。 算术和寄存器数据是32位，但存储器操作数的大小是可变的。 存储器操作数的大小由指令指定。 根据本发明的指令允许在单个固定长度指令中的多个存储器操作数。 指令集小而简单，所以执行成本比传统处理器低。 提供了更多的寻址模式，从而创建了更有效的代码。 信号量使用单个位实现。 移位和合并指令用于访问跨越边界的数据。
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10.发明授权公开(公告)号：US06434689B1
公开(公告)日：2002-08-13
申请号：US09189111
申请日：1998-11-09
申请人： Rod G. Fleck , Roger D. Arnold , Bruce Holmer , Danielle G. Lemay
发明人： Rod G. Fleck , Roger D. Arnold , Bruce Holmer , Danielle G. Lemay
IPC分类号： G06F1500
摘要： An apparatus is described that comprises a data processing unit and at least one coprocessor. The data processing unit comprises a register file having registers, a memory, a plurality of execution units, a coprocessor interface for coupling the at least one coprocessor with the data processing unit, and a pipeline configuration for processing instructions having a fetch stage for fetching an instruction from the memory, a decode stage for decoding an operational code from the instruction, an execution stage for activating one of the execution units, and a write-back stage for God writing back from the execution unit. The data processing unit comprises read-and write-lines coupling the register file with the coprocessor for exchanging operands, at least one control line indicating that the coprocessor is busy, and a plurality of control lines from the decode stage for controlling the coprocessor which are operated upon detection of a coprocessor instruction. The coprocessor is using the registers from the register file during execution of the coprocessor instruction. The coprocessor comprises a decode unit for decoding the coprocessor instruction and a plurality of coprocessor execution units that share the decode unit, the decode unit selects one of the coprocessor execution units upon the coprocessor instruction, and the selected one of the coprocessor execution units performs the coprocessor instruction.
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