公开(公告)号：US06813209B2

公开(公告)日：2004-11-02

申请号：US10685371

申请日：2003-10-14

申请人： Ethan A. Crain ,  Karl Rapp ,  Etan Shacham

发明人： Ethan A. Crain ,  Karl Rapp ,  Etan Shacham

IPC分类号： G11C702

CPC分类号： G11C7/067 ,  G11C7/062 ,  G11C2207/063

摘要： A low read current, low power consumption sense amplifier well suited for low frequency RFID systems is disclosed. An MOS transistor receives the read current from a memory cell, typically an EEPROM, and a current mirror is formed by a parallel MOS transistor. The mirror current is integrated on a capacitor after the charge on the capacitor is cleared via a reset pulse. A time period is defined during which the voltage on the capacitor is compared to a second voltage. The second voltage is formed from a reference voltage or from dummy cells, in either case the reference voltage is at about the logic boundary between a one and zero stored in a memory cell. A comparator, with or without input hysteresis, receives the voltage on the capacitor and a second voltage and within the time period, the output state of the comparator indicates the binary contents of the memory cell.

摘要翻译： 公开了一种非常适合低频RFID系统的低读电流，低功耗读出放大器。 MOS晶体管从存储单元（通常为EEPROM）接收读取电流，电流镜由并联MOS晶体管形成。 电容器上的电荷通过复位脉冲清零后，镜电流集成在电容上。 定义一个时间段，在该时间段期间将电容器上的电压与第二电压进行比较。 第二电压由参考电压或虚设单元形成，在任一种情况下，参考电压约为存储在存储单元中的一个和零之间的逻辑边界。 具有或不具有输入滞后的比较器接收电容器上的电压和第二电压，并且在该时间段内，比较器的输出状态指示存储器单元的二进制内容。

公开(公告)号：US06781460B2

公开(公告)日：2004-08-24

申请号：US10282569

申请日：2002-10-29

申请人： Ethan A. Crain ,  Pravas Pradhan

发明人： Ethan A. Crain ,  Pravas Pradhan

IPC分类号： H03F345

CPC分类号： H03F3/45219 ,  H03F3/45192

摘要： A folder common cascode circuit with symmetric parallel signal paths from the differential inputs to the differential outputs provides a low skew, low jitter, low power differential amplifier. The signal paths on either side of the differential amplifier are made equal with equal loads along each path. Pairs of complementary NMOS and PMOS transistor pairs with parallel complementary biasing stacks on the output cascode circuitry maintain symmetrical parallel signal paths, amplification and impedance loading from differential input to differential output. Output voltage translating inverters provide a higher voltage level output signal while maintaining low skew and jitter.

摘要翻译： 具有从差分输入到差分输出的对称并行信号路径的文件夹共用共源共栅电路提供了低偏移，低抖动，低功耗差分放大器。 差分放大器两侧的信号路径在沿着每个路径的相等载荷下相等。 成对的互补NMOS和PMOS晶体管对，在输出共源共栅电路上具有并联互补偏置堆叠，保持对称的并行信号路径，从差分输入到差分输出的放大和阻抗负载。 输出电压转换逆变器提供更高的电压电平输出信号，同时保持低的偏移和抖动。