公开(公告)号：US08912823B2

公开(公告)日：2014-12-16

申请号：US13992885

申请日：2011-12-08

申请人： Venkatesh Rao ,  Alok Shah ,  Pravas Pradhan

发明人： Venkatesh Rao ,  Alok Shah ,  Pravas Pradhan

IPC分类号： H03K19/0185 ,  H03K19/00 ,  H03K19/003

CPC分类号： H03K19/018521 ,  H03K19/0013 ,  H03K19/00384

摘要： Described herein is a voltage compensated level-shifter with nearly constant duty cycle and matching rise and fall slopes of the output of the level-shifter, no meta-stability, and nearly constant propagation delay across power supply levels. The voltage compensated level-shifter comprises a first inverter to receive an input signal for level shifting from a first power supply level to a second power supply level, and to generate a first inverted signal, the first inverter operating on the first power supply level; a second inverter to receive the input signal and to generate a second inverted signal, the second inverter operating on the second power supply level; and a NOR logical gate to receive the first and second inverted signals and to generate an output signal, the NOR logical gate operating on the second power supply level, wherein the output signal is level shifted to the second power supply level.

摘要翻译： 这里描述的是电压补偿电平移位器，其具有几乎恒定的占空比并且匹配电平转换器的输出的上升和下降斜率，没有元稳定性以及跨供电电平几乎恒定的传播延迟。 电压补偿电平转换器包括：第一反相器，用于接收用于从第一电源电平到第二电源电平的电平转换的输入信号;以及产生第一反相信号，所述第一反相器在第一电源电平上工作; 第二逆变器，用于接收所述输入信号并产生第二反相信号，所述第二逆变器在所述第二电源电平上工作; 以及NOR逻辑门，用于接收第一和第二反相信号并产生输出信号，NOR逻辑门在第二电源电平上工作，其中输出信号电平移位到第二电源电平。

公开(公告)号：US07154307B2

公开(公告)日：2006-12-26

申请号：US10720857

申请日：2003-11-24

申请人： Pravas Pradhan ,  Jianhong Ju

发明人： Pravas Pradhan ,  Jianhong Ju

IPC分类号： H03K5/22 ,  H03K5/153

CPC分类号： H04L25/0272 ,  H04L25/0278 ,  H04L25/0282 ,  H04L25/0294

摘要： A current mode transfer logic system suitable for driving transmission lines is disclosed. In one embodiment a twisted pair transmission line is terminated in its characteristic line impedance. A signal is formed of two unequal currents, preferably of different polarities as well as magnitudes, that are driven down the two lines. The unequal currents are selectively switched between the two lines creating a logic signal of a differential current drive of unequal current magnitudes. The unequal currents are received and shunted from the distal end of each line via diode connected MOS transistors. The MOS transistors are biased to present a low impedance, but an impedance higher than the terminating resistor. The currents are amplified and converted to useable CMOS voltage levels. In another embodiment the twisted pair is replaced by two parallel transmission lines which are terminated in one resistor, equal to the sum of the characteristic impedances of each line. The terminating resistor is connected between the distal signal carrying conductors of each transmission line. The shields or return paths for each line are tied together at the distal and at the proximate (drive) ends of the line.

摘要翻译： 公开了适用于驱动传输线的电流模式传输逻辑系统。 在一个实施例中，双绞线传输线在其特征线阻抗中终止。 信号由两条不相等的电流形成，优选地具有不同的极性以及在两条线路上被驱动的幅度。 在两条线之间选择性地切换不相等的电流，从而产生不等电流幅值的差动电流驱动的逻辑信号。 通过二极管连接的MOS晶体管，从每条线的远端接收不相等的电流并分流。 MOS晶体管被偏置以呈现低阻抗，但阻抗高于终端电阻器。 电流被放大并转换成可用的CMOS电压电平。 在另一个实施例中，双绞线被两个平行的传输线代替，这两条并行传输线终止于一个电阻器中，等于每条线路的特征阻抗之和。 终端电阻连接在每条传输线的远端信号承载导体之间。 每条线的屏蔽或返回路径在线的远端和近端（驱动）端连接在一起。

公开(公告)号：US06870424B2

公开(公告)日：2005-03-22

申请号：US10645408

申请日：2003-08-21

申请人： Pravas Pradhan ,  Shailesh Chitnis

发明人： Pravas Pradhan ,  Shailesh Chitnis

IPC分类号： H03F3/45

CPC分类号： H03F3/45192 ,  H03F3/45219

摘要： A folded common cascode circuit with symmetric parallel signal paths from the differential inputs to a single ended output provides a low skew, low jitter, low power, high speed differential in/out amplifier. There is a differential input stage followed by a load or current summation stage with all gates tied together, and then a second differential stage. The dynamic voltage range of the second stage allows for lower Vcc operation while providing improved jitter operation. The signal paths on either side of the differential amplifier are made equal with equal loads along each path. Pairs of complementary NMOS and PMOS transistor pairs with parallel complementary biasing current mirroring stacks on the cascode circuitry have all their gates connected together. The layout maintains symmetrical parallel signal paths and symmetrical amplification and impedance loading from differential input to the differential output. Output inverters provide a higher drive capability.

摘要翻译： 具有从差分输入到单端输出的对称并行信号路径的折叠共用共源共栅电路提供低偏移，低抖动，低功耗，高速差分输入/输出放大器。 存在差分输入级，随后是负载或电流求和级，所有门连接在一起，然后是第二差分级。 第二级的动态电压范围允许较低的Vcc操作，同时提供改善的抖动操作。 差分放大器两侧的信号路径在沿着每个路径的相等载荷下相等。 在共源共栅电路上具有并联互补偏置电流镜像叠层的互补NMOS和PMOS晶体管对的对具有连接在一起的所有栅极。 该布局保持对称的并行信号路径以及从差分输入到差分输出的对称放大和阻抗负载。 输出逆变器提供更高的驱动能力。

公开(公告)号：US06970043B2

公开(公告)日：2005-11-29

申请号：US10645033

申请日：2003-08-21

申请人： Pravas Pradhan ,  Shailesh Chitnis

发明人： Pravas Pradhan ,  Shailesh Chitnis

IPC分类号： H03F3/45

CPC分类号： H03F3/45192 ,  H03F3/45219

摘要： A folded common cascode circuit with symmetric parallel signal paths from the differential inputs to a single ended output provides a low skew, low jitter, low power, high speed differential amplifier. The signal paths on either side of the differential amplifier are made equal with equal loads along each path. Pairs of complementary NMOS and PMOS transistor pairs with parallel complementary biasing current mirroring stacks on the cascode circuitry have all their gates connected together. The layout maintains symmetrical parallel signal paths and symmetrical amplification and impedance loading from differential input to output. Output inverters provide a higher drive capability.

摘要翻译： 具有从差分输入到单端输出的对称并行信号路径的折叠共用共源共栅电路提供了低偏移，低抖动，低功耗，高速差分放大器。 差分放大器两侧的信号路径在沿着每个路径的相等载荷下相等。 在共源共栅电路上具有并联互补偏置电流镜像叠层的互补NMOS和PMOS晶体管对的对具有连接在一起的所有栅极。 布局维持对称的并行信号路径和对称的放大和差分输入到输出的阻抗负载。 输出逆变器提供更高的驱动能力。

公开(公告)号：US20150092065A1

公开(公告)日：2015-04-02

申请号：US14040044

申请日：2013-09-27

申请人： Prakash Radhakrishnan ,  Sathyanarayanan Gopal ,  Pravas Pradhan ,  Aruna Kumar

发明人： Prakash Radhakrishnan ,  Sathyanarayanan Gopal ,  Pravas Pradhan ,  Aruna Kumar

IPC分类号： H04N17/00

CPC分类号： H04N21/43632 ,  G09G5/006 ,  G09G2330/021 ,  G09G2330/12 ,  G09G2370/10

摘要： A method for training the lanes of a main data link includes setting an initial lane voltage swing and conducting link at the initial value, and determining if link training was successful. If link training at the initial value of lane voltage swing was not successful, the value of lane voltage swing is incremented to a predetermined value. A determination is made as to whether the predetermined value of lane voltage swing exceeds a threshold value, and link training is ended if the predetermined value of lane voltage exceeds the threshold value. If the predetermined value of lane voltage swing does not exceed the threshold value, link training is conducted at the predetermined value of lane voltage swing until link training is successful or until a predetermined number of attempts at the predetermined value of lane voltage swing fail to successfully train the link.

摘要翻译： 用于训练主数据链路的通道的方法包括：将初始车道电压摆幅设置为初始值，并确定链路训练是否成功。 如果车道电压摆幅初始值的链路训练不成功，则车道电压摆幅的值增加到规定值。 确定车道电压摆幅的预定值是否超过阈值，并且如果车道电压的预定值超过阈值，则链接训练结束。 如果车道电压摆幅的预定值不超过阈值，则以车道电压摆幅的预定值进行链路训练，直到链路训练成功或直到预定次数的车道电压摆幅的尝试失败成功 训练链接。

公开(公告)号：US20150085187A1

公开(公告)日：2015-03-26

申请号：US14032846

申请日：2013-09-20

申请人： Huimin Chen ,  George R. Hayek ,  Robert Jamie Johnston ,  Pravas Pradhan ,  Satyanarayana Avadhanam ,  Seh W. Kwa

发明人： Huimin Chen ,  George R. Hayek ,  Robert Jamie Johnston ,  Pravas Pradhan ,  Satyanarayana Avadhanam ,  Seh W. Kwa

IPC分类号： H04N5/63 ,  H04N5/38 ,  H04N5/44 ,  H04N7/01

CPC分类号： H04N5/63 ,  G09G5/003 ,  G09G5/006 ,  G09G5/36 ,  G09G2320/103 ,  G09G2330/021 ,  G09G2340/02 ,  G09G2360/18 ,  G09G2370/04 ,  G09G2370/10 ,  H04N5/38 ,  H04N5/44 ,  H04N7/0127 ,  H04N21/4122 ,  H04N21/43632

摘要： An electronic device, method, and at least one machine readable medium for burst mode processing of video data with inband link power management are provided herein. The method includes receiving a pixel stream, transferring the received stream as currently-available frame-formatted video data to a sink in burst at high data rate, and entering a reduced-power operating state until transfer of additional currently-available video data is enabled. The method may include issuing inband command signals to cause the link to enter into and exit from the reduced-power link operating states.

摘要翻译： 本文提供了一种用于具有带内链路功率管理的视频数据的突发模式处理的电子设备，方法和至少一个机器可读介质。 该方法包括接收像素流，将接收的流作为当前可用的帧格式的视频数据以高数据速率突发传送到接收器，并进入降低功率的操作状态，直到启用额外的当前可用视频数据的传输 。 该方法可以包括发出带内命令信号以使链路进入和退出低功率链路工作状态。

公开(公告)号：US20090172056A1

公开(公告)日：2009-07-02

申请号：US11967716

申请日：2007-12-31

申请人： Pravas Pradhan ,  Andrew M. Volk ,  Praveen Dani

发明人： Pravas Pradhan ,  Andrew M. Volk ,  Praveen Dani

IPC分类号： G06F7/58

CPC分类号： G06F7/588 ,  H04L9/0662 ,  H04L9/0861 ,  H04L2209/08 ,  H04L2209/12

摘要： Generally, this disclosure describes a system and method for generating random numbers. In at least one embodiment described herein, the method may include generating random bits in accordance with at least one security application via an integrated circuit, said integrated circuit including a true random number generator having an analog core. The method may further include providing, via an internally generated power supply, power to said analog core via a voltage regulator associated with said true random number generator. Of course, additional operations are also within the scope of the present disclosure.

摘要翻译： 通常，本公开描述了用于生成随机数的系统和方法。 在本文描述的至少一个实施例中，该方法可以包括经由集成电路根据至少一个安全应用产生随机比特，所述集成电路包括具有模拟核心的真随机数发生器。 该方法还可以包括经由内部产生的电源经由与所述真随机数发生器相关联的电压调节器向所述模拟核心提供电力。 当然，额外的操作也在本公开的范围内。

公开(公告)号：US20150134985A1

公开(公告)日：2015-05-14

申请号：US14074985

申请日：2013-11-08

申请人： Sathyanarayanan Gopal ,  Sanjib Basu ,  Pravas Pradhan ,  Prakash K. Radhakrishnan

发明人： Sathyanarayanan Gopal ,  Sanjib Basu ,  Pravas Pradhan ,  Prakash K. Radhakrishnan

IPC分类号： G06F1/32

CPC分类号： G06F1/3265 ,  G06F1/26 ,  G06F1/32 ,  G06F1/3287 ,  Y02D10/153 ,  Y02D10/171

摘要： By partitioning the source PHY of a physical layer interface, such as a DisplayPort interface, between multiple power domains, dynamic switching between various power modes with faster entry and exit latency can be achieved in some embodiments. In some embodiments, the scheme may be hardware initiated and autonomous in nature. A controller can switch the PHY in and out of the various power consumption modes, dependent on usage scenarios.

摘要翻译： 通过在多个功率域之间划分物理层接口（例如DisplayPort接口）的源PHY，可以在一些实施例中实现具有更快进入和退出延迟的各种功率模式之间的动态切换。 在一些实施例中，该方案本质上可以是硬件启动的和自主的。 根据使用情况，控制器可以切换PHY进出各种功耗模式。

公开(公告)号：US20130321026A1

公开(公告)日：2013-12-05

申请号：US13992885

申请日：2011-12-08

申请人： Venkatesh Rao ,  Alok Shah ,  Pravas Pradhan

发明人： Venkatesh Rao ,  Alok Shah ,  Pravas Pradhan

IPC分类号： H03K19/0185

CPC分类号： H03K19/018521 ,  H03K19/0013 ,  H03K19/00384

摘要： Described herein is a voltage compensated level-shifter with nearly constant duty cycle and matching rise and fall slopes of the output of the level-shifter, no meta-stability, and nearly constant propagation delay across power supply levels. The voltage compensated level-shifter comprises a first inverter to receive an input signal for level shifting from a first power supply level to a second power supply level, and to generate a first inverted signal, the first inverter operating on the first power supply level; a second inverter to receive the input signal and to generate a second inverted signal, the second inverter operating on the second power supply level; and a NOR logical gate to receive the first and second inverted signals and to generate an output signal, the NOR logical gate operating on the second power supply level, wherein the output signal is level shifted to the second power supply level.

摘要翻译： 这里描述的是电压补偿电平移位器，其具有几乎恒定的占空比并且匹配电平转换器的输出的上升和下降斜率，没有元稳定性以及跨供电电平几乎恒定的传播延迟。 电压补偿电平转换器包括：第一反相器，用于接收用于从第一电源电平到第二电源电平的电平转换的输入信号;以及产生第一反相信号，所述第一反相器在第一电源电平上工作; 第二逆变器，用于接收所述输入信号并产生第二反相信号，所述第二逆变器在所述第二电源电平上工作; 以及NOR逻辑门，用于接收第一和第二反相信号并产生输出信号，NOR逻辑门在第二电源电平上工作，其中输出信号电平移位到第二电源电平。

公开(公告)号：US08595274B2

公开(公告)日：2013-11-26

申请号：US11967716

申请日：2007-12-31

申请人： Pravas Pradhan ,  Andrew M. Volk ,  Praveen Dani

发明人： Pravas Pradhan ,  Andrew M. Volk ,  Praveen Dani

IPC分类号： G06F1/02

CPC分类号： G06F7/588 ,  H04L9/0662 ,  H04L9/0861 ,  H04L2209/08 ,  H04L2209/12

摘要： Generally, this disclosure describes a system and method for generating random numbers. In at least one embodiment described herein, the method may include generating random bits in accordance with at least one security application via an integrated circuit, said integrated circuit including a true random number generator having an analog core. The method may further include providing, via an internally generated power supply, power to said analog core via a voltage regulator associated with said true random number generator. Of course, additional operations are also within the scope of the present disclosure.

摘要翻译： 通常，本公开描述了用于生成随机数的系统和方法。 在本文描述的至少一个实施例中，该方法可以包括经由集成电路根据至少一个安全应用产生随机比特，所述集成电路包括具有模拟核心的真随机数发生器。 该方法还可以包括经由内部产生的电源经由与所述真随机数发生器相关联的电压调节器向所述模拟核心提供电力。 当然，额外的操作也在本公开的范围内。