公开(公告)号：US4654789A

公开(公告)日：1987-03-31

申请号：US596756

申请日：1984-04-04

申请人： Eugene Nusinov ,  John J. Bradley

发明人： Eugene Nusinov ,  John J. Bradley

IPC分类号： G06F1/22 ,  G06F12/06 ,  G06F1/00 ,  G06F13/00

CPC分类号： G06F12/0623 ,  G06F1/22 ,  H01L2924/0002

摘要： A chip implemented in newer technology is designed to include new functionality. The chip includes compatibility circuits which connect to a pin which is unused in the chip it replaces in an existing computer system. The compatibility circuits connect to those internal parts of the new chip that contain the newly added or altered functionality. The new chip is installed in the existing computer system just as the prior chip. When so installed, the compatibility circuits enable the new chip to operate in the same manner as the replaced chip but at higher speed and with improved performance. When the new chip is installed in the system for which it was designed, the compatibility circuits enable the chip to operate with the new functionality at the same higher speed and improved performance as compared to the replaced chip.

摘要翻译： 以较新技术实现的芯片旨在包括新功能。 该芯片包括连接到在现有计算机系统中替代的芯片中未使用的引脚的兼容性电路。 兼容性电路连接到包含新添加或改变的功能的新芯片的内部部分。 新芯片就像以前的芯片一样安装在现有的计算机系统中。 当这样安装时，兼容性电路使新芯片能够以与更换的芯片相同的方式工作，但是以更高的速度和更好的性能。 当新芯片安装在其设计的系统中时，兼容性电路使得芯片能够以与更换的芯片相同的更高速度和更高的性能与新的功能一起运行。

公开(公告)号：US5053951A

公开(公告)日：1991-10-01

申请号：US331054

申请日：1989-03-28

申请人： Eugene Nusinov ,  Thomas F. Joyce

发明人： Eugene Nusinov ,  Thomas F. Joyce

IPC分类号： G06F12/10 ,  G06F12/14

CPC分类号： G06F12/1036 ,  G06F12/145 ,  Y02B60/1225

摘要： A segment descriptor unit (SDU) includes a divided random access memory (RAM), a content addressable memory (CAM) and decoder circuits interconnected for performing dynamic and static address translation operations within a minimum of chip area and power. The CAM is arranged to store a number of entries which include segment number and validity information associated with a corresponding number of segment descriptors. The RAM contains locations allocated for storing segment descriptor words (SDW's) and working data. Each SDW is logically divided into two fields, a static translation word (STW) field containing all of the bits required for performing a static address translation operation and an access control word (ACW) field containing all of the bits required for verifying compliance with system security. The bits of each STW and ACW are stored in alternate bit positions of the SDW locations. Each pair of RAM bit locations couple to a common read/write amplifier and multiplexer circuit. Through the use of microinstruction commands coded to specify different address translation functions, the STW and ACW fields selected by the CAM are read out from RAM during different intervals for carrying out the steps of those operations.

摘要翻译： 段描述符单元（SDU）包括分离的随机存取存储器（RAM），内容可寻址存储器（CAM）和互连的解码器电路，用于在最小的芯片面积和功率内执行动态和静态地址转换操作。 CAM被设置为存储多个条目，其包括与相应数量的段描述符相关联的段号和有效性信息。 RAM包含分配用于存储段描述符字（SDW）和工作数据的位置。 每个SDW在逻辑上分为两个字段，一个包含执行静态地址转换操作所需的所有位的静态转换字（STW）字段和包含用于验证系统符合性所需的所有位的访问控制字（ACW）字段 安全。 每个STW和ACW的位被存储在SDW位置的交替位位置。 每对RAM位位置耦合到公共读/写放大器和多路复用器电路。 通过使用编码的微指令命令来指定不同的地址转换功能，在不同间隔期间，从RAM中选择的STW和ACW字段从RAM中读出，以执行这些操作的步骤。

公开(公告)号：US4813002A

公开(公告)日：1989-03-14

申请号：US887768

申请日：1986-07-21

申请人： Thomas F. Joyce ,  Eugene Nusinov ,  Richard P. Brown

发明人： Thomas F. Joyce ,  Eugene Nusinov ,  Richard P. Brown

IPC分类号： G06F12/10 ,  G11C15/04 ,  G11C15/00

CPC分类号： G06F12/1027 ,  G11C15/04

摘要： A translator is organized to include at least a pair of content addressable memories (CAMs), each for storing a different portion of the total number of bits of each of the words to be translated. The outputs from each CAM are logically combined within a multiple input random access memory (RAM). Both CAMs are interrogated simultaneously and deliver the results of comparing the word portions of an input word and the CAM contents to the RAM in substantially less time then required for a single CAM memory. The results are logically combined with in the RAM which, in response to a match condition, delivers the results of the translation as an output.

摘要翻译： 翻译器被组织成包括至少一对内容可寻址存储器（CAM），每个存储器可用于存储要翻译的每个字的总位数的不同部分。 每个CAM的输出在逻辑上组合在一个多输入随机存取存储器（RAM）中。 两个CAM被同时询问并且将输入字和CAM内容的字部分与RAM相比较的结果，在单个CAM存储器所需要的时间上要少得多。 结果在逻辑上与RAM相结合，RAM响应于匹配条件将转换的结果传递为输出。