公开(公告)号：US20100160274A1

公开(公告)日：2010-06-24

申请号：US12716468

申请日：2010-03-03

Applicant: Sharon Sageman ,  Richard P. Brown

Inventor： Sharon Sageman ,  Richard P. Brown

IPC: A61K31/56 ,  A61P25/24 ,  A61P25/22 ,  A61P25/08 ,  A61P25/26

CPC classification number: A61K31/56 ,  A61K31/5685

Abstract: The present invention relates to the use of 3-acetyl-7-oxo-dehydroepiandrosterone (7-keto DHEA) in the preparation of a medicament to treat or ameliorate psychiatric conditions. The present invention relates to methods of using compositions comprising 7-keto DHEA to treat or ameliorate psychiatric conditions. These methods include administering an effective amount of a composition comprising 7-keto DHEA in an acceptable carrier, alone or in combination with other psychiatric drugs to reduce or ameliorate symptoms of a psychiatric condition. This method may be used alone or as an adjunctive treatment for treating a wide variety of psychiatric conditions.

Abstract translation: 本发明涉及3-乙酰基-7-氧代 - 脱氢表雄酮（7-酮DHEA）在制备治疗或改善精神病状的药物中的用途。 本发明涉及使用包含7-酮DHEA的组合物来治疗或改善精神病症的方法。 这些方法包括在可接受的载体中单独或与其它精神药物组合施用有效量的包含7-酮DHEA的组合物，以减少或改善精神状态的症状。 该方法可以单独使用或用作治疗各种精神病状的辅助治疗。

公开(公告)号：US5430862A

公开(公告)日：1995-07-04

申请号：US546348

申请日：1990-06-29

Applicant: Steven S. Smith ,  Arnold J. Smith ,  Amy E. Gilfeather ,  Richard P. Brown ,  Thomas F. Joyce

Inventor： Steven S. Smith ,  Arnold J. Smith ,  Amy E. Gilfeather ,  Richard P. Brown ,  Thomas F. Joyce

IPC: G06F9/318 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3804 ,  G06F9/30174 ,  G06F9/3879

Abstract: The emulator includes first and second pipelined stages connected through a bidirectional bus for executing source instructions normally executed by a different/source computer in a highly overlapped manner. The first stage includes an emulator chip which performs the function of fetching and decoding each source instruction stored in cache memory resulting in the generation of a number of vector addresses required for executing the instruction by the second stage. The second stage includes a high performance microprocessor chip having on-chip instruction and data caches for storing a plurality of emulation subroutines and data fetched during subroutine execution. In pipelined fashion, the emulator chip fetches and decodes each source instruction which generates a vector branch address which is loaded into the branch vector register while the microprocessor chip fetches and executes emulation subroutines specified by the vector address transferred via the bus for each previously decoded source instruction.

Abstract translation: 仿真器包括通过双向总线连接的第一和第二流水线级，用于执行通常由高度重叠的方式由不同/源计算机执行的源指令。 第一级包括仿真器芯片，其执行取出和解码存储在高速缓冲存储器中的每个源指令的功能，导致生成由第二级执行指令所需的多个向量地址。 第二级包括具有片上指令的高性能微处理器芯片和用于存储多个仿真子程序的数据高速缓存和在子程序执行期间取出的数据。 以流水线方式，仿真器芯片获取和解码每个源指令，其产生载入分支向量寄存器的向量分支地址，而微处理器芯片从每个先前解码的源获取并执行由总线传送的向量地址指定的仿真子程序 指令。

公开(公告)号：US4424561A

公开(公告)日：1984-01-03

申请号：US221854

申请日：1980-12-31

Applicant: Philip E. Stanley ,  Richard P. Brown ,  Arthur Peters

Inventor： Philip E. Stanley ,  Richard P. Brown ,  Arthur Peters

IPC: G06F12/08 ,  G06F13/00 ,  G06F13/06

CPC classification number: G06F12/0851

Abstract: A cache memory for use in a data processing system wherein data words identified by even address numbers are stored separately from data words associated with odd address numbers to enable the simultaneous transfer of two successively addressed data words to or from the cache memory by the transferring of a data word associated with an odd address number and a data word associated with an even address number.

Abstract translation: 一种在数据处理系统中使用的高速缓存存储器，其中由偶数地址号码识别的数据字与与奇数地址号码相关联的数据字分开存储，以使得能够通过传送 与奇数地址号码相关联的数据字和与偶数地址号码相关联的数据字。

公开(公告)号：US4389549A

公开(公告)日：1983-06-21

申请号：US323919

申请日：1981-11-23

Applicant: Richard P. Brown

Inventor： Richard P. Brown

IPC: H01H1/58 ,  H01H21/30 ,  H01H23/00 ,  H01H19/04

CPC classification number: H01H23/006 ,  H01H1/5805 ,  H01H21/30

Abstract: A miniature DIP switch (10) has actuator levers (82) projecting from a side of the housing (12). A plurality of cantilevered moveable contact arms (72) are supported by a section (34) of the base (30), and a plurality of oppositely disposed cantilevered contact arms (62) are supported by a complementary section (32) of the base. A plurality of insulative rotatable lever actuators (80) are supported each by a respective moveable contact arm (72). Each actuator (80) comprises a lever (82) projecting from a respective opening (18) In the housing (12), an arcuate bearing surface (86) engaging an arcuately shaped boss (22) in the housing, a pair of depending side walls (88) each having arcuately shaped ends (90), and a cam protrusion (87) disposed between the depending side walls (88) and engaging its respective moveable contact arm (72). Rotation of the actuator (80) about the arcuately shaped boss (22) causes slideable engagement of the cam protrusion (87) with the moveable contact arm (72) whereby the moveable contact arm (72) is biased into engagement with its respective contact arm (62). A detent notch (77) in each moveable contact arm (72) provides a positive detent "feel" and "snap" upon engagement of the cam protrusion (87) with the notch (77).

Abstract translation: 小型DIP开关（10）具有从壳体（12）的一侧突出的致动器杆（82）。 多个悬臂可移动接触臂（72）由基座（30）的部分（34）支撑，并且多个相对设置的悬臂式接触臂（62）由基座的互补部分（32）支撑。 多个绝缘可旋转杆致动器（80）由相应的可移动接触臂（72）支撑。 每个致动器（80）包括从相应的开口（18）突出的杠杆（82），在壳体（12）中，与壳体中的弧形凸起（22）接合的弓形支承表面（86），一对悬垂侧 每个具有弓形端部（90）的壁（88）和设置在悬挂侧壁（88）之间并与其相应的可移动接触臂（72）接合的凸轮突起（87）。 致动器（80）围绕弓形凸起（22）的旋转导致凸轮突起（87）与可动触头臂（72）的滑动接合，由此可动接触臂（72）被偏置成与其相应的接触臂 （62）。 每个可移动接触臂（72）中的棘爪凹口（77）在凸轮突起（87）与凹口（77）接合时提供正的定位“触感”和“卡扣”。

公开(公告)号：US4323967A

公开(公告)日：1982-04-06

申请号：US140622

申请日：1980-04-15

Applicant: Arthur Peters ,  Virendra S. Negi ,  David E. Cushing ,  Richard P. Brown ,  Thomas F. Joyce

Inventor： Arthur Peters ,  Virendra S. Negi ,  David E. Cushing ,  Richard P. Brown ,  Thomas F. Joyce

IPC: G06F9/46 ,  G06F12/08 ,  G06F13/36 ,  G06F13/364 ,  G06F13/40 ,  G06F3/00

CPC classification number: G06F13/364 ,  G06F12/084 ,  G06F13/4059

Abstract: In a data processing system, a central subsystem includes a plurality of special purpose processing units with one of the processing units serving as a control processing unit within a central subsystem. The processing units are coupled to a common subsystem bus for the transfer of data, control information, and address information within the central subsystem. Access to the subsystem bus is allocated by a bus control unit which also interfaces the central subsystem with other processing units such as a system memory or system I/O devices that are included in the data processing system.

Abstract translation: 在数据处理系统中，中央子系统包括多个专用处理单元，其中一个处理单元用作中央子系统内的控制处理单元。 处理单元耦合到公共子系统总线，用于在中央子系统内传送数据，控制信息和地址信息。 子系统总线的访问由总线控制单元分配，总线控制单元还将中央子系统与诸如包括在数据处理系统中的系统存储器或系统I / O设备的其他处理单元接口。

公开(公告)号：US631692A

公开(公告)日：1899-08-22

申请号：US1899721243

申请日：1899-06-20

Applicant: EMIL MARKS ,  RICHARD P BROWN ,  BREEDING JOHN W

Inventor： BREEDING JOHN W

CPC classification number: B60B1/08 ,  B22D15/005

公开(公告)号：US08124598B2

公开(公告)日：2012-02-28

申请号：US11851761

申请日：2007-09-07

Applicant: Sharon Sageman ,  Richard P. Brown

Inventor： Sharon Sageman ,  Richard P. Brown

IPC: A61K31/56 ,  C07J1/00

CPC classification number: A61K31/56 ,  A61K31/5685

Abstract: The present invention comprises novel methods for the use of compositions comprising 7-keto DHEA for treating psychiatric conditions. These methods include administering an effective amount of a composition comprising 7-keto DHEA in an acceptable carrier, alone or in combination with other psychiatric drugs, such as analgesic agents, anticonvulsants, anti-anxiety agents, antidepressants, anti-panic agents, antipsychotic agents, bipolar agents, psychostimulants to reduce or ameliorate symptoms of a psychiatric condition. This method may be used alone or as an adjunctive treatment for treating a wide variety of psychiatric conditions such as stress disorders, anxiety disorders and depressive disorders.

Abstract translation: 本发明包括使用包含7-酮DHEA的组合物用于治疗精神病症的新方法。 这些方法包括在可接受的载体中单独或与其它精神病药物如镇痛剂，抗惊厥剂，抗焦虑剂，抗抑郁药，抗惊慌药，抗精神病药物组合使用有效量的包含7-酮DHEA的组合物 ，双相药物，精神兴奋剂以减轻或改善精神状况的症状。 该方法可以单独使用或作为治疗各种精神病症状的辅助治疗，例如应激障碍，焦虑障碍和抑郁障碍。

公开(公告)号：US5287522A

公开(公告)日：1994-02-15

申请号：US546347

申请日：1990-06-29

Applicant: Richard P. Brown ,  Thomas F. Joyce ,  Steven S. Smith

Inventor： Richard P. Brown ,  Thomas F. Joyce ,  Steven S. Smith

IPC: G06F9/38 ,  G06F13/24 ,  G06F13/14 ,  G06F9/00

CPC classification number: G06F9/3879 ,  G06F13/24 ,  G06F9/3861

Abstract: A system includes first and second processing units which are interconnected by a bidirectional bus. The first processing unit is a microprocessor chip programmed for executing procedures stored in an on-chip instruction cache unit. The second processing unit receives requests from an external source such as a system bus. The microprocessor chip includes a branch vector facility which connects to the bus. The second processing unit in response to an external request, generates a vector branch address. The processing unit transfers the vector branch address to the branch vector facility for storage along with setting a write indicator. The microprocessor chip, upon detecting that the write indicator was set, branches to the procedure specified by the branch vector address for executing the instructions of the procedure to carry out those operations required for processing the external request or event.

Abstract translation: 系统包括通过双向总线互连的第一和第二处理单元。 第一处理单元是被编程用于执行存储在片上指令高速缓存单元中的程序的微处理器芯片。 第二处理单元从诸如系统总线的外部源接收请求。 微处理器芯片包括连接到总线的分支向量设备。 第二处理单元响应于外部请求，生成向量分支地址。 处理单元将向量分支地址传送到分支向量设备以便存储，同时设置写入指示符。 微处理器芯片在检测到写入指示符被设置后，分支到由分支向量地址指定的过程，用于执行该过程的指令以执行处理外部请求或事件所需的那些操作。

公开(公告)号：US4392201A

公开(公告)日：1983-07-05

申请号：US221855

申请日：1980-12-31

Applicant: Richard P. Brown ,  George J. Barlow ,  Arthur Peters

Inventor： Richard P. Brown ,  George J. Barlow ,  Arthur Peters

IPC: G06F12/08 ,  G11C29/26 ,  G06F13/00 ,  G06F13/06

CPC classification number: G06F12/0851 ,  G11C29/26

Abstract: A cache memory wherein data words identified by odd address numbers are stored separately from data words identified by even address numbers. A group of diagnostic control registers supply signals for controlling the testing of the cache within the cache memory to determine the operability of the individual elements included in the cache memory.

Abstract translation: 高速缓冲存储器，其中由奇数地址号码识别的数据字与偶数地址号码识别的数据字分开存储。 一组诊断控制寄存器提供用于控制高速缓冲存储器内的高速缓存测试的信号，以确定包含在高速缓冲存储器中的各个元件的可操作性。

公开(公告)号：US4371928A

公开(公告)日：1983-02-01

申请号：US140623

申请日：1980-04-15

Applicant: George J. Barlow ,  Philip E. Stanley ,  Richard P. Brown

Inventor： George J. Barlow ,  Philip E. Stanley ,  Richard P. Brown

IPC: G06F12/06 ,  G06F12/04 ,  G06F13/16 ,  G06F13/36 ,  G06F13/00

CPC classification number: G06F12/04 ,  G06F13/1678

Abstract: In a data processing system, a system memory includes first memory modules having a data path of a first bit width and second memory modules having a data path of a second bit width with the first bit width being less than the second bit width. A central subsystem includes a cache memory unit and processing units for initiating requests for data transfers of the second bit width between the system memory and the subsystem processing units. An interface coupling the system memory and the central subsystem for bidirectional data transfers generates, in response to a memory request of a second bit width wherein the requested data is stored in a first memory module, additional memory requests until sufficient data has been retrieved from the system memory to satisfy the central subsystem request. The interface also monitors data transfers between the system processing units and the system memory and transfers the data transfers to the central subsystem in order to update and to retain the integrity of the cache memory in the central subsystem.

Abstract translation: 在数据处理系统中，系统存储器包括具有第一位宽度的数据路径的第一存储器模块和具有第二位宽度的数据路径的第二存储器模块，第一位宽小于第二位宽度。 中央子系统包括高速缓冲存储器单元和处理单元，用于启动系统存储器和子系统处理单元之间的第二位宽的数据传输请求。 耦合系统存储器和用于双向数据传输的中央子系统的接口响应于第二位宽度的存储器请求而产生其中所请求的数据存储在第一存储器模块中的附加存储器请求，直到从 系统内存以满足中央子系统的要求。 该接口还监视系统处理单元和系统存储器之间的数据传输，并将数据传输传送到中央子系统，以便更新并保持高速缓冲存储器在中央子系统中的完整性。