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公开(公告)号:US07557033B2
公开(公告)日:2009-07-07
申请号:US11647087
申请日:2006-12-27
申请人: Eun Soo Kim , Seung Hee Hong , Cheol Mo Jeong , Jung Geun Kim
发明人: Eun Soo Kim , Seung Hee Hong , Cheol Mo Jeong , Jung Geun Kim
IPC分类号: H01L21/4763
CPC分类号: H01L21/76834 , H01L21/32139 , H01L21/76837
摘要: A method of forming a metal line of a semiconductor memory device includes the steps of forming plugs of a damascene structure in a first interlayer insulating layer over a semiconductor substrate, forming a barrier metal layer, a metal layer and an anti-reflection layer on the resulting surface, etching the anti-reflection layer, the metal layer, and the barrier metal layer according a specific pattern, and forming an insulating layer on sidewalls of the metal layer.
摘要翻译: 形成半导体存储器件的金属线的方法包括以下步骤:在半导体衬底上的第一层间绝缘层中形成镶嵌结构的插塞,在其上形成阻挡金属层,金属层和抗反射层 根据特定图案蚀刻抗反射层,金属层和阻挡金属层,并在金属层的侧壁上形成绝缘层。
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公开(公告)号:US20080146023A1
公开(公告)日:2008-06-19
申请号:US11753543
申请日:2007-05-24
申请人: Seung Hee HONG , Cheol Mo Jeong , Jung Geun Kim , Eun Soo Kim
发明人: Seung Hee HONG , Cheol Mo Jeong , Jung Geun Kim , Eun Soo Kim
IPC分类号: H01L21/44
CPC分类号: H01L21/28562 , H01L21/32131 , H01L21/76879 , H01L21/76882
摘要: A method of forming a metal wire in a semiconductor device includes performing a first etching process on an insulating layer formed on a semiconductor substrate to form a trench and an insulating layer pattern, the insulating layer pattern defining the trench. A barrier metal layer is formed over the insulating layer pattern and the trench. A second etching process is performed on the barrier metal layer to expose upper corners of the trench while leaving the trench substantially covered with the barrier metal layer. A metal layer is formed over the barrier metal layer in the trench. A heat treatment process is performed for reflowing the metal layer. The metal layer is planarized.
摘要翻译: 在半导体器件中形成金属线的方法包括对形成在半导体衬底上的绝缘层进行第一蚀刻工艺以形成沟槽和绝缘层图案,绝缘层图案限定沟槽。 在绝缘层图案和沟槽之上形成阻挡金属层。 在阻挡金属层上进行第二蚀刻工艺以暴露沟槽的上角,同时留下基本上被阻挡金属层覆盖的沟槽。 在沟槽中的阻挡金属层的上方形成有金属层。 进行用于回流金属层的热处理工艺。 金属层被平坦化。
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公开(公告)号:US20080081453A1
公开(公告)日:2008-04-03
申请号:US11603752
申请日:2006-11-22
申请人: Jung Geun Kim , Cheol Mo Jeong , Eun Soo Kim , Seung Hee Hong
发明人: Jung Geun Kim , Cheol Mo Jeong , Eun Soo Kim , Seung Hee Hong
IPC分类号: H01L21/44
CPC分类号: H01L21/76831 , H01L21/76843 , H01L21/76876 , H01L21/7688
摘要: A method of forming a metal line of a semiconductor device includes the steps of forming an insulating layer and a glue layer on a semiconductor substrate, removing a portion of the glue layer and the insulating layer to form trenches, forming a metal layer over the semiconductor substrate including the trenches and the glue layer, and performing a polishing process until the insulating layer is exposed, thus forming a metal line.
摘要翻译: 形成半导体器件的金属线的方法包括以下步骤:在半导体衬底上形成绝缘层和胶层,去除一部分胶层和绝缘层以形成沟槽,在半导体上形成金属层 包括沟槽和胶层的衬底,并且进行抛光工艺直到绝缘层露出,从而形成金属线。
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公开(公告)号:US20080003814A1
公开(公告)日:2008-01-03
申请号:US11647087
申请日:2006-12-27
申请人: Eun Soo Kim , Seung Hee Hong , Cheol Mo Jeong , Jung Geun Kim
发明人: Eun Soo Kim , Seung Hee Hong , Cheol Mo Jeong , Jung Geun Kim
IPC分类号: H01L21/44
CPC分类号: H01L21/76834 , H01L21/32139 , H01L21/76837
摘要: A method of forming a metal line of a semiconductor memory device includes the steps of forming plugs of a damascene structure in a first interlayer insulating layer over a semiconductor substrate, forming a barrier metal layer, a metal layer and an anti-reflection layer on the resulting surface, etching the anti-reflection layer, the metal layer, and the barrier metal layer according a specific pattern, and forming an insulating layer on sidewalls of the metal layer.
摘要翻译: 形成半导体存储器件的金属线的方法包括以下步骤:在半导体衬底上的第一层间绝缘层中形成镶嵌结构的插塞,在其上形成阻挡金属层,金属层和抗反射层 根据特定图案蚀刻抗反射层,金属层和阻挡金属层,并在金属层的侧壁上形成绝缘层。
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公开(公告)号:US07517793B2
公开(公告)日:2009-04-14
申请号:US11753543
申请日:2007-05-24
申请人: Seung Hee Hong , Cheol Mo Jeong , Jung Geun Kim , Eun Soo Kim
发明人: Seung Hee Hong , Cheol Mo Jeong , Jung Geun Kim , Eun Soo Kim
IPC分类号: H01L21/4763
CPC分类号: H01L21/28562 , H01L21/32131 , H01L21/76879 , H01L21/76882
摘要: A method of forming a metal wire in a semiconductor device includes performing a first etching process on an insulating layer formed on a semiconductor substrate to form a trench and an insulating layer pattern, the insulating layer pattern defining the trench. A barrier metal layer is formed over the insulating layer pattern and the trench. A second etching process is performed on the barrier metal layer to expose upper corners of the trench while leaving the trench substantially covered with the barrier metal layer. A metal layer is formed over the barrier metal layer in the trench. A heat treatment process is performed for reflowing the metal layer. The metal layer is planarized.
摘要翻译: 在半导体器件中形成金属线的方法包括对形成在半导体衬底上的绝缘层进行第一蚀刻工艺以形成沟槽和绝缘层图案,绝缘层图案限定沟槽。 在绝缘层图案和沟槽之上形成阻挡金属层。 在阻挡金属层上进行第二蚀刻工艺以暴露沟槽的上角,同时留下基本上被阻挡金属层覆盖的沟槽。 在沟槽中的阻挡金属层的上方形成有金属层。 进行用于回流金属层的热处理工艺。 金属层被平坦化。
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公开(公告)号:US07462536B2
公开(公告)日:2008-12-09
申请号:US11680500
申请日:2007-02-28
申请人: Cheol Mo Jeong , Whee Won Cho , Jung Geun Kim , Seung Hee Hong
发明人: Cheol Mo Jeong , Whee Won Cho , Jung Geun Kim , Seung Hee Hong
IPC分类号: H01L21/336
CPC分类号: H01L21/7684 , H01L27/10885
摘要: A method of forming a bit line of a semiconductor memory device is performed as follows. A first interlayer insulating layer is formed over a semiconductor substrate in which an underlying structure is formed. A region of the first interlayer insulating layer is etched to form contact holes through which a contact region of the semiconductor substrate is exposed. A low-resistance tungsten layer is deposited on the entire surface including the contact holes, thus forming contacts. A CMP process is performed in order to mitigate surface roughness of the low-resistance tungsten layer. The low-resistance tungsten layer on the interlayer insulating layer is patterned in a bit line metal line pattern, forming a bit line.
摘要翻译: 如下进行形成半导体存储器件的位线的方法。 第一层间绝缘层形成在形成下面的结构的半导体衬底上。 蚀刻第一层间绝缘层的区域以形成暴露半导体衬底的接触区域的接触孔。 在包括接触孔的整个表面上沉积低电阻钨层,从而形成接触。 执行CMP工艺以减轻低电阻钨层的表面粗糙度。 将层间绝缘层上的低电阻钨层图案化为位线金属线图案,形成位线。
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公开(公告)号:US20080057688A1
公开(公告)日:2008-03-06
申请号:US11680500
申请日:2007-02-28
申请人: Cheol Mo JEONG , Whee Won Cho , Jung Geun Kim , Seung Hee Hong
发明人: Cheol Mo JEONG , Whee Won Cho , Jung Geun Kim , Seung Hee Hong
IPC分类号: H01L21/3205
CPC分类号: H01L21/7684 , H01L27/10885
摘要: A method of forming a bit line of a semiconductor memory device is performed as follows. A first interlayer insulating layer is formed over a semiconductor substrate in which an underlying structure is formed. A region of the first interlayer insulating layer is etched to form contact holes through which a contact region of the semiconductor substrate is exposed. A low-resistance tungsten layer is deposited on the entire surface including the contact holes, thus forming contacts. A CMP process is performed in order to mitigate surface roughness of the low-resistance tungsten layer. The low-resistance tungsten layer on the interlayer insulating layer is patterned in a bit line metal line pattern, forming a bit line.
摘要翻译: 如下进行形成半导体存储器件的位线的方法。 第一层间绝缘层形成在形成下面的结构的半导体衬底上。 蚀刻第一层间绝缘层的区域以形成暴露半导体衬底的接触区域的接触孔。 在包括接触孔的整个表面上沉积低电阻钨层,从而形成接触。 执行CMP工艺以减轻低电阻钨层的表面粗糙度。 将层间绝缘层上的低电阻钨层图案化为位线金属线图案,形成位线。
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公开(公告)号:US20090053889A1
公开(公告)日:2009-02-26
申请号:US12053488
申请日:2008-03-21
申请人: Seung Hee Hong , Jung Geun Kim , Eun Soo Kim
发明人: Seung Hee Hong , Jung Geun Kim , Eun Soo Kim
IPC分类号: H01L21/4763
CPC分类号: H01L21/76877 , H01L21/76844 , H01L21/76846 , H01L21/76847 , H01L23/485 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要: A semiconductor device includes contact plugs formed in contact holes defined in an interlayer dielectric. Upper portions of the contact plugs are etched. A first barrier layer is formed on a surface of the interlayer dielectric including the contact plugs. A second barrier layer is formed on the first barrier layer over the interlayer dielectric. The second barrier layer has lower compatibility with a metallic material than the first barrier layer. A first metal layer is formed over the first and second barrier layers. The first metal layer, the first barrier layer and the second barrier layer are then patterned.
摘要翻译: 半导体器件包括形成在层间电介质中限定的接触孔中的接触塞。 接触塞的上部被蚀刻。 在包括接触塞的层间电介质的表面上形成第一阻挡层。 在层间电介质上的第一阻挡层上形成第二阻挡层。 与第一阻挡层相比,第二阻挡层与金属材料的相容性较低。 在第一和第二阻挡层上形成第一金属层。 然后对第一金属层,第一阻挡层和第二阻挡层进行图案化。
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公开(公告)号:US07713867B2
公开(公告)日:2010-05-11
申请号:US12053488
申请日:2008-03-21
申请人: Seung Hee Hong , Jung Geun Kim , Eun Soo Kim
发明人: Seung Hee Hong , Jung Geun Kim , Eun Soo Kim
IPC分类号: H01L21/4763
CPC分类号: H01L21/76877 , H01L21/76844 , H01L21/76846 , H01L21/76847 , H01L23/485 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要: A semiconductor device includes contact plugs formed in contact holes defined in an interlayer dielectric. Upper portions of the contact plugs are etched. A first barrier layer is formed on a surface of the interlayer dielectric including the contact plugs. A second barrier layer is formed on the first barrier layer over the interlayer dielectric. The second barrier layer has lower compatibility with a metallic material than the first barrier layer. A first metal layer is formed over the first and second barrier layers. The first metal layer, the first barrier layer and the second barrier layer are then patterned.
摘要翻译: 半导体器件包括形成在层间电介质中限定的接触孔中的接触塞。 接触塞的上部被蚀刻。 在包括接触塞的层间电介质的表面上形成第一阻挡层。 在层间电介质上的第一阻挡层上形成第二阻挡层。 与第一阻挡层相比,第二阻挡层与金属材料的相容性较低。 在第一和第二阻挡层上形成第一金属层。 然后对第一金属层,第一阻挡层和第二阻挡层进行图案化。
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公开(公告)号:US20090004817A1
公开(公告)日:2009-01-01
申请号:US11955881
申请日:2007-12-13
申请人: Jung Geun Kim , Eun Soo Kim , Seung Hee Hong , Suk Joong Kim
发明人: Jung Geun Kim , Eun Soo Kim , Seung Hee Hong , Suk Joong Kim
IPC分类号: H01L21/76
CPC分类号: H01L21/76232
摘要: A method of forming an isolation layer of a semiconductor device is disclosed herein, the method comprising the steps of providing a semiconductor substrate in which a tunnel insulating layer and a charge storage layer are formed on an active area and a trench is formed on an isolation area; forming a first insulating layer for filling a lower portion of the trench; forming a porous second insulating layer on the first insulating layer for filling a space between the charge storage layers; forming a third insulating layer on a side wall of the trench and the second insulating layer, the third insulating layer having a density higher than that of the second insulating layer; and forming a porous fourth insulating layer for filling the trench.
摘要翻译: 本文公开了形成半导体器件的隔离层的方法,该方法包括以下步骤:提供在有源区上形成隧道绝缘层和电荷存储层的半导体衬底,并且在隔离层上形成沟槽 区; 形成用于填充沟槽的下部的第一绝缘层; 在所述第一绝缘层上形成多孔第二绝缘层,用于填充所述电荷存储层之间的空间; 在所述沟槽和所述第二绝缘层的侧壁上形成第三绝缘层,所述第三绝缘层的密度高于所述第二绝缘层的密度; 以及形成用于填充所述沟槽的多孔第四绝缘层。
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