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1.发明申请Using at least one servo channel to provide timing recovery and timing information to data channels 失效使用至少一个伺服通道来向数据通道提供定时恢复和定时信息公开(公告)号：US20070177292A1
公开(公告)日：2007-08-02
申请号：US11346391
申请日：2006-02-01
申请人： Nhan Bui , Giovanni Cherubini , Evangelos Eleftheriou , Robert Hutchins , Glen Jaquette , Jens Jelitto , Sedat Oelcer , Mark Taylor
发明人： Nhan Bui , Giovanni Cherubini , Evangelos Eleftheriou , Robert Hutchins , Glen Jaquette , Jens Jelitto , Sedat Oelcer , Mark Taylor
IPC分类号： G11B5/09
CPC分类号： G11B27/36 , G11B20/10037 , G11B20/10046 , G11B20/10055 , G11B20/10212 , G11B20/10259 , G11B20/1403 , G11B20/1876 , G11B27/10 , G11B2020/10592 , G11B2220/90 , G11B2220/95
摘要： Provided is a read channel, storage drive, and method to process signals read from a storage medium. At least one data channel including an interpolator and equalizer and a servo channel includes an interpolator. A timing recovery function processes a timing error from the interpolator in the servo channel to calculate interpolation timing information used by the interpolator to interpolate a servo channel signal. A path is coupled to the timing recovery function and the interpolator in the at least one data channel to communicate the interpolation timing information to the interpolator in the at least one data channel. The interpolator in the at least one data channel is configured to use the interpolation timing information to interpolate an asynchronous data channel signal.
摘要翻译： 提供了一种用于处理从存储介质读取的信号的读通道，存储驱动器和方法。 包括内插器和均衡器和伺服信道的至少一个数据信道包括内插器。 定时恢复功能处理来自伺服信道中的内插器的定时误差，以计算内插器使用的内插定时信息来内插伺服信道信号。 路径耦合到至少一个数据信道中的定时恢复功能和内插器，以将内插定时信息传送到至少一个数据信道中的内插器。 所述至少一个数据信道中的内插器被配置为使用内插定时信息来内插异步数据信道信号。
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公开(公告)号：US20070076313A1
公开(公告)日：2007-04-05
申请号：US11242343
申请日：2005-10-03
IPC分类号： G11B5/09
CPC分类号： G11B5/09 , G11B2005/0013
摘要： Provided is a dynamic method for asymmetry compensation in a storage read channel. An asymmetry cancellation component in communication with an analog-to-digital converter receives an analog signal representing data read from a storage medium by a read head. The asymmetry cancellation component receives a digital signal from the analog-to-digital converter representing data read from the storage medium and computes an error signal indicating an asymmetry in the digital signal. The computed error signal is used to determine a coefficient. The digital signal is adjusted using the coefficient to produce a corrected digital signal.
摘要翻译： 提供了一种用于存储读取通道中的不对称补偿的动态方法。 与模数转换器通信的不对称消除部件接收表示由读取头从存储介质读取的数据的模拟信号。 不对称消除部件从模数转换器接收表示从存储介质读取的数据的数字信号，并计算指示数字信号不对称的误差信号。 计算出的误差信号用于确定系数。 使用系数调整数字信号以产生校正的数字信号。
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3.发明申请Magnetic tape read channel signal values developed employing intermediate bits of the path memory of a PRML viterbi detector 失效使用PRML维特比检测器的路径存储器的中间位开发的磁带读取通道信号值公开(公告)号：US20060119964A1
公开(公告)日：2006-06-08
申请号：US11003316
申请日：2004-12-03
CPC分类号： G11B20/10009 , G11B20/10037 , G11B20/10055 , G11B20/10074 , G11B20/10296 , G11B2220/90
摘要： Magnetic tape read channel signal values are developed employing intermediate bits of the path memory of a PRML Viterbi detector. Identification logic identifies a most likely path memory state of the PRML Viterbi detector from the path metrics of the PRML Viterbi detector. An intermediate bit sequence of the identified most likely path memory state is obtained, the intermediate bit sequence extending from an initiation point of the path memory which is intermediate the output and the input of the PRML Viterbi detector. A sample value is determined which corresponds to the obtained intermediate bit sequence.
摘要翻译： 使用PRML维特比检测器的路径存储器的中间位来开发磁带读取通道信号值。 识别逻辑根据PRML维特比检测器的路径度量来识别PRML维特比检测器的最可能的路径存储状态。 获得所识别的最可能的路径存储器状态的中间比特序列，从位于PRML维特比检测器的输出和输入之间的路径存储器的起始点延伸的中间比特序列。 确定对应于获得的中间位序列的采样值。
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公开(公告)号：US20070206310A1
公开(公告)日：2007-09-06
申请号：US11733934
申请日：2007-04-11
IPC分类号： G11B5/035
摘要： A read channel equalizer of a magnetic tape drive which equalized digitally sampled magnetic signals detected by a read head is dynamically adapted. A detector of equalizer dynamic adaptation logic compares equalizer output signals to desired values that are based on the decoding scheme (such as +2, 0 and −2 for PR4) to sense equalizer output signals that are offset from at least one desired value, and signals the fact of each offset and it polarity as amplitude independent error signals. The signaled sensed amplitude independent error signals are fed back to adjustable taps of the equalizer. The simplified error signals thus avoid complex calculations of waveform errors, such as least mean square calculations. The error signals may be weighted and may be adjusted to align synchronously provided error signals with asynchronous taps of the equalizer.
摘要翻译： 驱动磁头驱动器的读取通道均衡器，其均衡由读取头检测到的数字采样的磁信号。 均衡器动态适配逻辑的检测器将均衡器输出信号与基于解码方案（例如PR4的+2,0和-2）的期望值进行比较，以感测与至少一个期望值偏移的均衡器输出信号，以及 将每个偏移的事实表示为与振幅无关的误差信号。 信号感知的与振幅无关的误差信号反馈到均衡器的可调节抽头。 因此，简化的误差信号避免了波形误差的复杂计算，例如最小均方根计算。 误差信号可以被加权并且可以被调整以使同步提供的误差信号与均衡器的异步抽头对齐。
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5.发明申请Apparatus, system, and method for adaptive asynchronous equalization using leakage 有权使用泄漏进行自适应异步均衡的装置，系统和方法公开(公告)号：US20070098061A1
公开(公告)日：2007-05-03
申请号：US11263189
申请日：2005-10-31
CPC分类号： G11B20/10009 , G11B20/10046 , G11B20/10175 , G11B20/10481 , H04L25/03019 , H04L2025/03484 , H04L2025/03681
摘要： An apparatus, system, and method are disclosed for adaptive asynchronous equalization using leakage. An equalizer sums products of a plurality of tap signals from a delay line sampling a read signal and a plurality of corresponding tap coefficients to form an equalized signal in an asynchronous time domain having a first sampling rate. A leaky function module calculates a leaky function for each tap coefficient in the asynchronous time domain. An adaptation module adapts each of the tap coefficients as the leaky function for each tap coefficient summed with a signal-dependent updating function for each tap coefficient.
摘要翻译： 公开了一种使用泄漏进行自适应异步均衡的装置，系统和方法。 均衡器对来自对读取信号进行采样的延迟线和多个对应抽头系数的多个抽头信号的乘积相加，以在具有第一采样率的异步时域中形成均衡信号。 泄漏功能模块计算异步时域中每个抽头系数的泄漏函数。 适配模块将每个抽头系数适配为每个抽头系数的泄漏函数，用于针对每个抽头系数的与信号相关的更新函数相加。
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公开(公告)号：US20070047127A1
公开(公告)日：2007-03-01
申请号：US11215409
申请日：2005-08-30
IPC分类号： G11B5/035
CPC分类号： G11B5/035 , G11B20/10046 , G11B20/10212 , G11B20/1201
摘要： Provided is a read channel incorporated in a storage device to process signals read from a storage medium. The read channel includes an equalizer equalizing input read signals to produce equalizer output signals. A detector senses an adjusted equalizer output signal to determine an output value comprising data represented by the input read signals. An equalizer adaptor receives the output value from the detector to determine a first error signal used to adjust the equalizer operations. A component adjusts the equalizer output signals being transmitted to the detector, wherein the component is adjusted by a second error signal calculated from the output value from the detector, wherein the first and second error signals are different.
摘要翻译： 提供了一种结合在存储装置中以读取从存储介质读取的信号的读通道。 读通道包括均衡器均衡输入读信号以产生均衡器输出信号。 检测器感测调整的均衡器输出信号以确定包括由输入读取信号表示的数据的输出值。 均衡器适配器从检测器接收输出值以确定用于调整均衡器操作的第一误差信号。 一个分量调整正被发送到检测器的均衡器输出信号，其中通过从检测器的输出值计算的第二误差信号调整分量，其中第一和第二误差信号是不同的。
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7.发明申请Method for a cyclic dibit response estimation in a media system using a data set separator sequence 失效在使用数据集分隔符序列的媒体系统中进行循环双位响应估计的方法公开(公告)号：US20060250719A1
公开(公告)日：2006-11-09
申请号：US11122680
申请日：2005-05-05
IPC分类号： G11B5/09
CPC分类号： G11B20/10 , G11B20/10009 , G11B20/10046
摘要： A dibit response estimation generator receives a DSS sequence and a DSS readback sequence, which is a function of a channel processing of the DSS sequence by a read channel. The generator generates a cyclic dibit response vector as a function of the DSS sequence and the DSS readback sequence. The generator further generates an error signal as a function of a comparison of the DSS readback sequence and a filtering of the DSS sequence based on the cyclic dibit response vector. An unacceptable error signal indicates a need to adjust the cyclic dibit response vector to yield an acceptable comparison of the DSS readback sequence and the filtering of the DSS sequence based on the cyclic dibit response vector.
摘要翻译： 双向响应估计生成器接收DSS序列和DSS回读序列，DSS序列是通过读取通道的DSS序列的信道处理的函数。 发生器产生作为DSS序列和DSS回读序列的函数的循环双位响应向量。 发生器还根据DSS回读序列的比较和基于循环双位响应向量的DSS序列的滤波产生误差信号。 不可接受的误差信号表示需要调整循环双位响应向量，以产生DSS回读序列的可接受比较和基于循环双位响应向量的DSS序列的过滤。
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公开(公告)号：US20060119969A1
公开(公告)日：2006-06-08
申请号：US11003283
申请日：2004-12-03
摘要： A read channel equalizer of a magnetic tape drive which equalizes digitally sampled magnetic signals detected by a read head is dynamically adapted. A detector of equalizer dynamic adaptation logic compares equalizer output signals to desired values that are based on the decoding scheme (such as +2, 0 and −2 for PR4) to sense equalizer output signals that are offset from at least one desired value, and signals the fact of each offset and its polarity as amplitude independent error signals. The signaled sensed amplitude independent error signals are fed back to adjustable taps of the equalizer. The simplified error signals thus avoid complex calculations of waveform errors, such as least mean square calculations. The error signals may be weighted and may be adjusted to align synchronously provided error signals with asynchronous taps of the equalizer.
摘要翻译： 磁头驱动器的读取通道均衡器，其均衡由读取头检测到的数字采样磁信号。 均衡器动态适配逻辑的检测器将均衡器输出信号与基于解码方案（例如PR4的+2,0和-2）的期望值进行比较，以感测与至少一个期望值偏移的均衡器输出信号，以及 将每个偏移及其极性的事实表示为与振幅无关的误差信号。 信号感知的与振幅无关的误差信号反馈到均衡器的可调节抽头。 因此，简化的误差信号避免了波形误差的复杂计算，例如最小均方根计算。 误差信号可以被加权并且可以被调整以使同步提供的误差信号与均衡器的异步抽头对齐。
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9.发明申请公开(公告)号：US20070115574A1
公开(公告)日：2007-05-24
申请号：US11286553
申请日：2005-11-23
CPC分类号： G11B20/10009 , G11B20/10046 , G11B20/10055 , G11B20/10074 , G11B20/10175
摘要： Provided is an asynchronous read channel shaped toward generalized partial response characteristics. The read channel is incorporated in a storage device to process signals read from a storage medium. An equalizer receives asynchronous input read signals and shapes the input read signals toward a desired fixed characteristic in an asynchronous time domain. An interpolator transforms the read signal from the equalizer in the asynchronous time domain to a synchronous time domain. A noise whitening filter processes the read signal shaped toward the desired fixed characteristic to produce an output read signal shaped towards a generalized partial response polynomial. A detector receives the read signal shaped towards the generalized partial response polynomial in the synchronous time domain to determine an output value comprising data represented by the input read signals.
摘要翻译： 提供了形成为广义部分响应特性的异步读取通道。 读取通道被结合在存储设备中以处理从存储介质读取的信号。 均衡器接收异步输入读取信号，并将输入读取信号形成为异步时域中期望的固定特性。 内插器将来自异步时域中的均衡器的读信号转换为同步时域。 噪声白化滤波器处理朝向期望的固定特性成形的读取信号，以产生朝向广义部分响应多项式成形的输出读取信号。 检测器接收在同步时域中形成为广义部分响应多项式的读信号，以确定包括由输入读信号表示的数据的输出值。
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10.发明申请Method for an equalizer computation in a media system using a data set separator sequence 有权在使用数据集分隔符序列的媒体系统中进行均衡器计算的方法公开(公告)号：US20060268442A1
公开(公告)日：2006-11-30
申请号：US11136872
申请日：2005-05-25
IPC分类号： G11B5/035
CPC分类号： G11B5/09 , G11B20/10009 , G11B20/10046 , G11B20/10481 , G11B2005/0013 , G11B2220/90
摘要： An equalizer coefficients generator receives a DSS sequence and a DSS readback sequence, which is a function of a channel processing of the DSS sequence by a read channel. The generator generates a coefficeint cyclic equalizer vector as a function of the DSS sequence and the DSS readback sequence. The generator further generates an error signal as a function of a comparison of the DSS sequence and an equalization of the DSS readback sequence based on the coefficeint cyclic equalizer vector. An unacceptable error signal indicates a need to adjust the coefficeint cyclic equalizer vector to yield an acceptable comparison of the DSS sequence and an equalization of the DSS readback sequence based on the coefficeint cyclic equalizer vector.
摘要翻译： 均衡器系数发生器接收DSS序列和DSS回读序列，DSS序列是通过读通道的DSS序列的信道处理的函数。 发生器根据DSS序列和DSS回读序列生成一个系数循环均衡器向量。 发生器还根据DSS序列的比较和基于系数循环均衡器向量的DSS回读序列的均衡来生成误差信号。 不可接受的错误信号指示需要调整系数循环均衡器向量以产生DSS序列的可接受的比较和基于系数循环均衡器向量的DSS回读序列的均衡。
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