公开(公告)号：US20150325275A1

公开(公告)日：2015-11-12

申请号：US14492687

申请日：2014-09-22

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Hao Wu ,  Song-Wen Yang ,  Zhao-Yong Zhang ,  Kun-Ti Lee

IPC: G11C8/08

CPC classification number: G11C8/08 ,  G11C5/145 ,  G11C5/147 ,  G11C29/028 ,  G11C2029/1202

Abstract: A memory includes a logic controller, a word line driver, a boost circuit, plural capacitor circuits, plural memory cores, plural selectors, and plural output drivers. The logic controller generates a word line enabling signal and a boost enabling signal. The word line driver receives the word line enabling signal. The boost circuit receives the boost enabling signal. The plural capacitor circuits are connected between the boost circuit and the word line driver. Each of the plural memory cores is connected with the word line driver through plural word lines. The plural selectors are connected with the corresponding memory cores. The plural output drivers are connected with the corresponding selectors. The number of the plural memory cores is positively correlated with the number of the plural capacitor circuits.

Abstract translation: 存储器包括逻辑控制器，字线驱动器，升压电路，多个电容器电路，多个存储器核，多个选择器和多个输出驱动器。 逻辑控制器产生字线使能信号和升压使能信号。 字线驱动器接收字线使能信号。 升压电路接收升压使能信号。 多个电容电路连接在升压电路和字线驱动器之间。 多个存储器核心中的每一个通过多个字线与字线驱动器连接。 多个选择器与相应的存储器核心连接。 多个输出驱动器与相应的选择器连接。 多个存储器核的数量与多个电容器电路的数量正相关。

公开(公告)号：US09177624B1

公开(公告)日：2015-11-03

申请号：US14492687

申请日：2014-09-22

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Hao Wu ,  Song-Wen Yang ,  Zhao-Yong Zhang ,  Kun-Ti Lee

IPC: G11C16/04 ,  G11C8/08 ,  G11C5/14

CPC classification number: G11C8/08 ,  G11C5/145 ,  G11C5/147 ,  G11C29/028 ,  G11C2029/1202

Abstract: A memory includes a logic controller, a word line driver, a boost circuit, plural capacitor circuits, plural memory cores, plural selectors, and plural output drivers. The logic controller generates a word line enabling signal and a boost enabling signal. The word line driver receives the word line enabling signal. The boost circuit receives the boost enabling signal. The plural capacitor circuits are connected between the boost circuit and the word line driver. Each of the plural memory cores is connected with the word line driver through plural word lines. The plural selectors are connected with the corresponding memory cores. The plural output drivers are connected with the corresponding selectors. The number of the plural memory cores is positively correlated with the number of the plural capacitor circuits.

Abstract translation: 存储器包括逻辑控制器，字线驱动器，升压电路，多个电容器电路，多个存储器核，多个选择器和多个输出驱动器。 逻辑控制器产生字线使能信号和升压使能信号。 字线驱动器接收字线使能信号。 升压电路接收升压使能信号。 多个电容电路连接在升压电路和字线驱动器之间。 多个存储器核心中的每一个通过多个字线与字线驱动器连接。 多个选择器与相应的存储器核心连接。 多个输出驱动器与相应的选择器连接。 多个存储器核的数量与多个电容器电路的数量正相关。

公开(公告)号：US09484085B1

公开(公告)日：2016-11-01

申请号：US15098329

申请日：2016-04-14

Applicant: Faraday Technology Corporation ,  Faraday Technology Corp.

Inventor： Zhao-Yong Zhang ,  Kun-Ti Lee

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: A static memory apparatus and a static memory cell thereof are provided. The static memory cell includes a data latch circuit, a data write-in circuit and a data read-out circuit. The data latch circuit has a first tristate output inverting circuit and a second tristate output inverting circuit. The data write-in circuit provides a first reference voltage to a power receiving terminal of a selected tristate output inverting circuit which is one of the first and second tristate output inverting circuits, and provides a second reference voltage to an input terminal of the selected tristate output inverting circuit during a data write-in time period. The data read-out circuit generates read-out data according to a voltage at an output terminal of the second tristate output inverting circuit and the second reference voltage during a data read-out time period.

Abstract translation: 提供了一种静态存储装置及其静态存储单元。 静态存储单元包括数据锁存电路，数据写入电路和数据读出电路。 数据锁存电路具有第一三态输出反相电路和第二三态输出反相电路。 数据写入电路向作为第一和第二三态输出反相电路之一的所选三态输出反相电路的功率接收端提供第一参考电压，并向所选三态输入端的输入端提供第二参考电压 在数据写入期间输出反相电路。 数据读出电路根据数据读出期间的第二三态输出反相电路的输出端的电压和第二基准电压来生成读出数据。