SEMICONDUCTOR PATTERNING
    1.
    发明申请

    公开(公告)号:US20210118912A1

    公开(公告)日:2021-04-22

    申请号:US16463670

    申请日:2017-11-28

    摘要: A technique of producing a stack defining a plurality of TFTs including at least source/drain electrodes and addressing lines at a source/drain level, wherein the method comprises: forming a patterned source/drain level stack comprising at least a first layer over the support substrate and a second layer over the first layer, to define at least said source/drain electrodes and said addressing lines; depositing semiconductor channel material over at least said source/drain electrodes and said addressing lines; and patterning the layer of semiconductor channel material by a patterning process; wherein the material of the first layer is more resistant to removal by said patterning process than the material of said second layer.

    SOURCE/DRAIN CONDUCTORS FOR TRANSISTOR DEVICES

    公开(公告)号:US20170213915A1

    公开(公告)日:2017-07-27

    申请号:US15039126

    申请日:2014-12-09

    摘要: A transistor device comprising: source and drain conductors connected by a semiconductor channel provided by a layer of semiconductor material formed over the source and drain conductors; and a gate conductor capacitively coupled to the semiconductor channel via a gate dielectric; wherein at least one of the source and drain conductors comprises a multilayer structure in at least one region thereof, the multilayer structure comprising a lower layer and an upper layer, the material of the lower layer being better than the material of the upper layer at injecting charge into the semiconductor material; and the material of the upper layer exhibiting better electrical conductivity than the material of the lower layer.