公开(公告)号：US20170250187A1

公开(公告)日：2017-08-31

申请号：US15521768

申请日：2015-10-09

申请人： Floadia Corporation

发明人： Yasuhiro TANIGUCHI ,  Hideo KASAI ,  Yasuhiko KAWASHIMA ,  Ryotaro SAKURAI ,  Yutaka SHINAGAWA ,  Kosuke OKUYAMA

IPC分类号： H01L27/112 ,  H01L27/06 ,  H01L27/108 ,  H01L27/11585 ,  H01L27/11502

CPC分类号： H01L27/11206 ,  G11C17/06 ,  G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L27/0629 ,  H01L27/10805 ,  H01L27/11502 ,  H01L27/11585

摘要： In an anti-fuse memory includes a rectifier element of a semiconductor junction structure in which a voltage applied from a memory gate electrode to a word line is applied as a reverse bias in accordance with voltage values of the memory gate electrode and the word line, and does not use a conventional control circuit. Hence, the rectifier element blocks application of a voltage from the memory gate electrode to the word line. Therefore a conventional switch transistor that selectively applies a voltage to a memory capacitor and a conventional switch control circuit allowing the switch transistor to turn on or off are not necessary. Miniaturization of the anti-fuse memory and a semiconductor memory device are achieved correspondingly.

公开(公告)号：US20180019248A1

公开(公告)日：2018-01-18

申请号：US15553465

申请日：2016-02-19

申请人： Floadia Corporation

发明人： Hideo KASAI ,  Yasuhiro TANIGUCHI ,  Yasuhiko KAWASHIMA ,  Ryotaro SAKURAI ,  Yutaka SHINAGAWA ,  Tatsuro TOYA ,  Takanori YAMAGUCHI ,  Fukuo OWADA ,  Shinji YOSHIDA ,  Teruo HATADA ,  Satoshi NODA ,  Takafumi KATO ,  Tetsuya MURAYA ,  Kosuke OKUYAMA

IPC分类号： H01L27/112 ,  H01L23/525

CPC分类号： H01L27/11206 ,  G11C17/16 ,  H01L23/5252

摘要： In a semiconductor memory device, voltage application from a memory gate electrode of the memory capacitor to a word line can be blocked by a rectifier element depending on values of voltages applied to the memory gate electrode and the word line without using a conventional control circuit. The configuration eliminates the need to provide a switch transistor and a switch control circuit for turning on and off the switch transistor as in conventional cases, and accordingly achieves downsizing. In the semiconductor memory device, for example, each bit line contact is shared by four anti-fuse memories adjacent to each other and each word line contact is shared by four anti-fuse memories adjacent to each other, thereby achieving downsizing of the entire device as compared to a case in which the bit line contact and the word line contact are individually provided to each anti-fuse memory.

公开(公告)号：US20180083014A1

公开(公告)日：2018-03-22

申请号：US15561774

申请日：2016-03-18

申请人： FLOADIA CORPORATION

发明人： Yutaka SHINAGAWA ,  Yasuhiro TANIGUCHI ,  Hideo KASAI ,  Ryotaro SAKURAI ,  Yasuhiko KAWASHIMA ,  Tatsuro TOYA ,  Kosuke OKUYAMA

IPC分类号： H01L27/11 ,  H01L29/792 ,  H01L29/788 ,  G11C11/412

CPC分类号： H01L27/1104 ,  G11C11/412 ,  G11C14/00 ,  H01L27/11 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

摘要： A non-volatile SRAM memory cell and a non-volatile semiconductor memory device capable of programming SRAM data in a SRAM to a non-volatile memory unit through fast operation of the SRAM are disclosed. A non-volatile semiconductor memory device can achieve reduction in a voltage necessary for a programming operation to program SRAM data to the non-volatile memory unit. Thus, a first access transistor, a second access transistor, a first load transistor, a second load transistor, a first drive transistor, and a second drive transistor included in the SRAM connected with the non-volatile memory unit can each include a gate insulating film having a thickness less than or equal to 4 nm, which achieves fast operation of the SRAM at a lower power supply voltage.