公开(公告)号：US20200303003A1

公开(公告)日：2020-09-24

申请号：US16769390

申请日：2019-07-25

申请人： FLOADIA CORPORATION

发明人： Kazumasa YANAGISAWA ,  Tomoichi HAYASHI ,  Satoshi NODA ,  Yasuhiro TANIGUCHI ,  Kosuke OKUYAMA

IPC分类号： G11C13/00 ,  G06F9/38

摘要： A multiply-accumulate operation apparatus is capable of sufficiently restraining a sneak current when employing a precharge method where the magnitude of an electric current flowing through an output line is detected. In a synapse operation section, memory cells storing respective synaptic connection weights are arranged in rows and columns. Output lines are connected to memory cells in the corresponding column, and input lines are connected to memory cells in the corresponding row. Each output line is precharged, and then its electric potential is decreased during the corresponding memory cells flow cell currents corresponding to their synaptic connection weights. A memory element of each memory cell includes a memory transistor, a drain side transistor, and a source side transistor connected in series, and is connected between the corresponding input and output line. The memory transistor stores a synaptic connection weight according to the amount of charge in a charge storage layer.

公开(公告)号：US20210183925A1

公开(公告)日：2021-06-17

申请号：US16760935

申请日：2018-12-26

申请人： FLOADIA CORPORATION

发明人： Shoji SHUKURI ,  Kazumasa YANAGISAWA ,  Toshifumi TAKEDA ,  Kosuke OKUYAMA ,  Yasuhiro TANIGUCHI

IPC分类号： H01L27/146 ,  H04N5/3745

摘要： The present invention provides a solid-state imaging device and a camera system capable of recording a still image without using a recording medium. Each pixel P of an image sensor is provided with a photodiode, a transfer transistor, a reset transistor, and an amplifying transistor, as well as a memory element that has functions of a select transistor. The memory element has a structure integrating a drain side select transistor, a source side select transistor, and a memory transistor. By applying a program voltage to a memory gate electrode as a gate voltage, the memory transistor stores charge of an amount corresponding to an amount of light received by the photodiode in a charge storage layer.

公开(公告)号：US20180211965A1

公开(公告)日：2018-07-26

申请号：US15744163

申请日：2016-07-21

申请人： FLOADIA CORPORATION

发明人： Shoji YOSHIDA ,  Fukuo OWADA ,  Daisuke OKADA ,  Yasuhiko KAWASHIMA ,  Shinji YOSHIDA ,  Kazumasa YANAGISAWA ,  Yasuhiro TANIGUCHI

IPC分类号： H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/28

CPC分类号： H01L27/115 ,  H01L21/28 ,  H01L27/10 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/792

摘要： A memory cell includes a memory gate structure, a first select gate structure, and a second select gate structure. In the memory gate structure, a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a metal memory gate electrode are stacked in this order. The first select gate structure includes a metal first select gate electrode along a first sidewall spacer provided on a sidewall of the memory gate structure. The second select gate structure includes a metal second select gate electrode along a second sidewall spacer provided on another sidewall of the memory gate structure. Thus, the metal memory gate electrode, the metal first select gate electrode, and the metal second select gate electrode can be formed of a same metallic material as a metal logic gate electrode, permitting the memory cell to be formed together with the metal logic gate electrode.

公开(公告)号：US20180083014A1

公开(公告)日：2018-03-22

申请号：US15561774

申请日：2016-03-18

申请人： FLOADIA CORPORATION

发明人： Yutaka SHINAGAWA ,  Yasuhiro TANIGUCHI ,  Hideo KASAI ,  Ryotaro SAKURAI ,  Yasuhiko KAWASHIMA ,  Tatsuro TOYA ,  Kosuke OKUYAMA

IPC分类号： H01L27/11 ,  H01L29/792 ,  H01L29/788 ,  G11C11/412

CPC分类号： H01L27/1104 ,  G11C11/412 ,  G11C14/00 ,  H01L27/11 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

摘要： A non-volatile SRAM memory cell and a non-volatile semiconductor memory device capable of programming SRAM data in a SRAM to a non-volatile memory unit through fast operation of the SRAM are disclosed. A non-volatile semiconductor memory device can achieve reduction in a voltage necessary for a programming operation to program SRAM data to the non-volatile memory unit. Thus, a first access transistor, a second access transistor, a first load transistor, a second load transistor, a first drive transistor, and a second drive transistor included in the SRAM connected with the non-volatile memory unit can each include a gate insulating film having a thickness less than or equal to 4 nm, which achieves fast operation of the SRAM at a lower power supply voltage.

公开(公告)号：US20200075105A1

公开(公告)日：2020-03-05

申请号：US16491704

申请日：2018-02-05

申请人： FLOADIA CORPORATION

发明人： Shinji YOSHIDA ,  Kazumasa YANAGISAWA ,  Shuichi SATO ,  Yasuhiro TANIGUCHI

IPC分类号： G11C16/24 ,  G11C16/04 ,  G11C16/10 ,  G11C16/28 ,  G11C16/30

摘要： A non-volatile semiconductor memory device that achieves downsizing as compared to conventional cases is disclosed. A non-volatile semiconductor memory device has a configuration in which a memory cell is disposed between a programming bit line and a reading bit line. The reading bit line provided between adjacent memory cells is shared by the adjacent memory cells. This configuration of the non-volatile semiconductor memory device, in which the reading bit line is shared by the adjacent memory cells, leads to reduction of the number of reading bit lines as compared to that in a conventional configuration, and further leads to reduction of the area of a control circuit and a sense amplifier circuit connected with the reading bit line, thereby achieving downsizing as compared to conventional cases accordingly.

公开(公告)号：US20170250187A1

公开(公告)日：2017-08-31

申请号：US15521768

申请日：2015-10-09

申请人： Floadia Corporation

发明人： Yasuhiro TANIGUCHI ,  Hideo KASAI ,  Yasuhiko KAWASHIMA ,  Ryotaro SAKURAI ,  Yutaka SHINAGAWA ,  Kosuke OKUYAMA

IPC分类号： H01L27/112 ,  H01L27/06 ,  H01L27/108 ,  H01L27/11585 ,  H01L27/11502

CPC分类号： H01L27/11206 ,  G11C17/06 ,  G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L27/0629 ,  H01L27/10805 ,  H01L27/11502 ,  H01L27/11585

摘要： In an anti-fuse memory includes a rectifier element of a semiconductor junction structure in which a voltage applied from a memory gate electrode to a word line is applied as a reverse bias in accordance with voltage values of the memory gate electrode and the word line, and does not use a conventional control circuit. Hence, the rectifier element blocks application of a voltage from the memory gate electrode to the word line. Therefore a conventional switch transistor that selectively applies a voltage to a memory capacitor and a conventional switch control circuit allowing the switch transistor to turn on or off are not necessary. Miniaturization of the anti-fuse memory and a semiconductor memory device are achieved correspondingly.

公开(公告)号：US20180308990A1

公开(公告)日：2018-10-25

申请号：US15570981

申请日：2016-04-26

申请人： FLOADIA CORPORATION

发明人： Fukuo OWADA ,  Yasuhiko KAWASHIMA ,  Shinji YOSHIDA ,  Yasuhiro TANIGUCHI ,  Kosuke OKUYAMA

IPC分类号： H01L29/792 ,  H01L21/28 ,  H01L27/11573 ,  H01L29/423 ,  H01L29/66 ,  G11C16/04

CPC分类号： H01L29/792 ,  G11C16/0425 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66833

摘要： A semiconductor integrated circuit device includes first and second select gate electrodes that are sidewall-shaped along sidewalls of a memory gate structure. With this configuration, the memory gate structure is not disposed on the first select gate electrode and the second select gate electrode. Accordingly, the memory gate structure the first select gate structure, and the second select gate structure can have equal heights, thereby achieving reduction in size as compared to a conventional case. In addition, a silicide layer on the first select gate electrode and a silicide layer on the second select gate electrode can be separated farther from a memory gate electrode by the thickness of a cap film. Accordingly, the silicide layers on the first select gate electrode and the second select gate electrode are unlikely to contact with the memory gate electrode, thereby preventing a short-circuit defect of the memory gate electrode.

公开(公告)号：US20180286875A1

公开(公告)日：2018-10-04

申请号：US15578413

申请日：2016-12-07

申请人： Floadia Corporation

发明人： Daisuke OKADA ,  Kazumasa YANAGISAWA ,  Fukuo OWADA ,  Shoji YOSHIDA ,  Yasuhiko KAWASHIMA ,  Shinji YOSHIDA ,  Yasuhiro TANIGUCHI ,  Kosuke OKUYAMA

IPC分类号： H01L27/11521 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11568 ,  H01L29/66

CPC分类号： H01L27/11521 ,  G11C16/04 ,  G11C16/0433 ,  G11C16/10 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/788 ,  H01L29/792

摘要： When a memory cell (MC) is downsized by reducing the distance between a drain region (12a) and a source region (12b) on the surface of a fin (S2) with a high impurity concentration inside the fin (S2), the shape of the fin (S2) can be set such that a potential difference between a memory gate electrode (MG) and the fin (S2) is reduced to suppress the occurrence of disturbance. Accordingly, the memory cell (MC) achieves downsizing and suppression of the occurrence of disturbance.

公开(公告)号：US20210257376A1

公开(公告)日：2021-08-19

申请号：US17232824

申请日：2021-04-16

申请人： Floadia Corporation

发明人： Daisuke OKADA ,  Kazumasa YANAGISAWA ,  Fukuo OWADA ,  Shoji YOSHIDA ,  Yasuhiko KAWASHIMA ,  Shinji YOSHIDA ,  Yasuhiro TANIGUCHI ,  Kosuke OKUYAMA

IPC分类号： H01L27/11521 ,  H01L29/792 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L27/115 ,  H01L21/8238 ,  H01L27/11524 ,  H01L27/1157 ,  G11C16/04 ,  H01L29/788 ,  H01L27/11568 ,  H01L29/78

摘要： In a semiconductor memory device, voltage application from a memory gate electrode of the memory capacitor to a word line can be blocked by a rectifier element depending on values of voltages applied to the memory gate electrode and the word line without using a conventional control circuit. The configuration eliminates the need to provide a switch transistor and a switch control circuit for turning on and off the switch transistor as in conventional cases, and accordingly achieves downsizing. In the semiconductor memory device, for example, each bit line contact is shared by four anti-fuse memories adjacent to each other and each word line contact is shared by four anti-fuse memories adjacent to each other, thereby achieving downsizing of the entire device as compared to a case in which the bit line contact and the word line contact are individually provided to each anti-fuse memory.

公开(公告)号：US20190296030A1

公开(公告)日：2019-09-26

申请号：US16434373

申请日：2019-06-07

申请人： Floadia Corporation

发明人： Daisuke OKADA ,  Kazumasa YANAGISAWA ,  Fukuo OWADA ,  Shoji YOSHIDA ,  Yasuhiko KAWASHIMA ,  Shinji YOSHIDA ,  Yasuhiro TANIGUCHI ,  Kosuke OKUYAMA

IPC分类号： H01L27/11521 ,  H01L21/28 ,  H01L29/66 ,  G11C16/04 ,  H01L29/788 ,  H01L29/792 ,  H01L29/423 ,  H01L29/78 ,  H01L27/11568

摘要： When a memory cell (MC) is downsized by reducing the distance between a drain region (12a) and a source region (12b) on the surface of a fin (S2) with a high impurity concentration inside the fin (S2), the shape of the fin (S2) can be set such that a potential difference between a memory gate electrode (MG) and the fin (S2) is reduced to suppress the occurrence of disturbance. Accordingly, the memory cell (MC) achieves downsizing and suppression of the occurrence of disturbance.