公开(公告)号：US09332567B1

公开(公告)日：2016-05-03

申请号：US14724738

申请日：2015-05-28

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Inayat Ali ,  Somvir Dahiya ,  Arvind Kaushik ,  Sachin Prakash

IPC: H04B7/00 ,  H04W72/12 ,  H04W24/04

CPC classification number: H04W24/04 ,  H04W88/02

Abstract: An integrated circuit (IC) in an unresponsive radio equipment (RE) node includes a common public radio interface (CPRI) controller, a processor, and a system reset controller that includes an L1 (Layer 1) reset controller. The CPRI controller generates a reset request signal based on a CPRI reset request received from an RE controller (REC). The L1 reset controller generates a traffic stop signal based on the reset request signal. The CPRI controller generates a traffic idle signal based on the traffic stop signal. The L1 reset controller receives the traffic idle signal before a predetermined time period and generates a system reset signal for resetting the processor, thereby recovering the unresponsive RE node without disrupting the network topology of a communication system that includes the REC and multiple RE nodes including the unresponsive RE node connected via a CPRI link.

Abstract translation: 无响应无线电设备（RE）节点中的集成电路（IC）包括公共无线电接口（CPRI）控制器，处理器和包括L1（层1）复位控制器的系统复位控制器）。 CPRI控制器基于从RE控制器（REC）接收到的CPRI复位请求产生复位请求信号。 L1复位控制器基于复位请求信号产生交通停止信号。 CPRI控制器基于交通停止信号产生流量空闲信号。 L1复位控制器在预定时间段之前接收业务空闲信号，并产生用于重置处理器的系统复位信号，从而恢复无响应的RE节点，而不会中断包括REC和包括REC的多个RE节点的通信系统的网络拓扑 无响应的RE节点通过CPRI链路连接。

公开(公告)号：US09490880B1

公开(公告)日：2016-11-08

申请号：US14989805

申请日：2016-01-07

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Raghavendra Srinivas ,  Apoorv Goel ,  Arvind Kaushik ,  Sachin Prakash

IPC: H04B7/04 ,  H04B1/3816 ,  H04L7/00

CPC classification number: G06F5/06 ,  G06F1/04 ,  H04J3/0685

Abstract: For a baseband digital front-end (BDFE) processor that communicates with one or more radio-frequency integrated circuit (RFIC) chips over two or more JESD-compliant links in a multi-antenna base station, the BDFE has JESD transmitters (TXs) and receivers (RXs) that transmit and receive data to and from the RFIC chips and a time-based generator (TBGEN) that generates sync and idle signals that ensure that the processing of the different JESD TXs and RXs are aligned in time for data associated with a single logical group of antennas. The TBGEN has hardware-based alignment circuitry that generates the sync and idle signals, thereby avoiding the latency and unpredictability inherent with software-based solutions.

Abstract translation: 对于在多天线基站中通过两个或多个JESD兼容链路上的一个或多个射频集成电路（RFIC）芯片进行通信的基带数字前端（BDFE）处理器，BDFE具有JESD发射机（TX） 以及向RFIC芯片发送数据和从RFIC芯片接收数据的接收器（RX）以及产生同步和空闲信号的基于时间的发生器（TBGEN），其确保不同JESD TX和RX的处理在时间上与数据相关联 具有单个逻辑组天线。 TBGEN具有基于硬件的对准电路，可生成同步和空闲信号，从而避免基于软件的解决方案固有的延迟和不可预测性。