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    Communication system for transmitting and receiving control frames
    1.
    发明授权
    Communication system for transmitting and receiving control frames 有权

    公开(公告)号：US10261924B2

    公开(公告)日：2019-04-16

    申请号：US15227834

    申请日：2016-08-03

    Applicant: FREESCALE SEMICONDUCTOR, INC.

    Inventor： Hemant Nautiyal ,  Rajan Kapoor ,  Arvind Kaushik ,  Puneet Khandelwal

    IPC: G06F13/24 ,  G06F13/42

    Abstract: A communication system for communicating control data between a processor and an interface includes configuration registers, a packet processor, an interrupt processor, a timing monitor, a configuration sampler, a control-frame processor, a mode selector, and a transceiver. The processor, timing monitor, and configuration sampler generate control data, a timing signal and frame structure data, respectively. The packet processor generates a transmit control configuration packet, which includes the control data. The control-frame processor inserts the transmit control configuration packet into a first control frame, outputs the control frame to the interface and extracts a receive-configuration packet from a second control frame for generating one or more interrupts. The mode selector generates mode and idle signals for determining the mode of the interface, based on the idle signal. In one implementation, the system uses JESD control frames to reduce GPIO pin usage.

    Apparatus for reception and detection of random access channel (RACH) data
    2.
    发明授权
    Apparatus for reception and detection of random access channel (RACH) data 有权

    公开(公告)号：US10070465B2

    公开(公告)日：2018-09-04

    申请号：US14975831

    申请日：2015-12-20

    Applicant: FREESCALE SEMICONDUCTOR, INC.

    Inventor： Girraj K. Agrawal ,  Arvind Kaushik ,  Vincent Martinez ,  Amrit P. Singh

    IPC: H04W74/08 ,  H04W72/12

    Abstract: An apparatus for reception and detection of RACH data in an LTE input signal includes a hardware accelerator that has a decimator that filters and down-samples the input signal, a first Fourier transform circuit that transforms the decimated signal from the time domain to the frequency domain, and a second transform circuit that multiplies the resulting signal by a complex Z-C sequence and performs an inverse Fourier transform (iFT) operation to transform the multiplied signal from the frequency domain to the time domain. A DSP performs a delay profile analysis operation on the signal resulting from the iFT operation.

    Configurable FIR filter with segmented cells
    3.
    发明授权
    Configurable FIR filter with segmented cells 有权

    公开(公告)号：US09893714B2

    公开(公告)日：2018-02-13

    申请号：US14841712

    申请日：2015-09-01

    Applicant: FREESCALE SEMICONDUCTOR, INC.

    Inventor： Akshat Mittal ,  Arvind Kaushik ,  Peter Z. Rashev ,  Amrit P. Singh

    IPC: G05D16/00 ,  H03H17/06 ,  H03H17/02

    CPC classification number: H03H17/06 ,  H03H17/0225 ,  H03H17/0294

    Abstract: A FIR filter includes segment cells, each of which is configurable as an interpolation filter, a decimation filter, a symmetric filter, or an asymmetric filter. Two or more of the segment cells are configurable to be cascaded to form an interpolation filter, a decimation filter, a symmetric filter, an asymmetric filter, a complex symmetric filter, or a complex asymmetric filter. The FIR filter includes registers corresponding to the segment cells for storing coefficient values of the corresponding segment cells. The FIR filter further includes control circuits corresponding to the segment cells for generating control signals.

    System and method for mapping control and user data
    4.
    发明授权
    System and method for mapping control and user data 有权

    公开(公告)号：US09785368B1

    公开(公告)日：2017-10-10

    申请号：US15218053

    申请日：2016-07-24

    Applicant: FREESCALE SEMICONDUCTOR, INC.

    Inventor： Ritika Sharma ,  Somvir Dahiya ,  Arvind Kaushik ,  Amrit P. Singh

    IPC: G06F3/06 ,  H04W8/22

    CPC classification number: G11C8/18 ,  G11C7/1006 ,  G11C8/04 ,  H04Q2213/00

    Abstract: A system for mapping control and user data includes a direction scanner, an address calculator, a collision detector, a buffer, and a mapper for mapping control and user data from a first memory to a second memory. The direction scanner determines the highest priority value of to a code word index. The address calculator calculates start and end addresses of the highest priority value. When an address from an address range, defined by the start and end addresses, is already mapped to other control data, the collision detector detects a collision and generates feedback data. The address calculator outputs modified start and end addresses based on the feedback data. When no collision is detected, the address calculator outputs the modified start and end addresses to the buffer. The mapper then maps the control and user data to the modified start and end addresses in the second memory.

    Hardware-based time alignment of wireless links
    5.
    发明授权
    Hardware-based time alignment of wireless links 有权
    无线链路的基于硬件的时间对齐

    公开(公告)号：US09490880B1

    公开(公告)日：2016-11-08

    申请号：US14989805

    申请日：2016-01-07

    Applicant: FREESCALE SEMICONDUCTOR, INC.

    Inventor： Raghavendra Srinivas ,  Apoorv Goel ,  Arvind Kaushik ,  Sachin Prakash

    IPC: H04B7/04 ,  H04B1/3816 ,  H04L7/00

    CPC classification number: G06F5/06 ,  G06F1/04 ,  H04J3/0685

    Abstract: For a baseband digital front-end (BDFE) processor that communicates with one or more radio-frequency integrated circuit (RFIC) chips over two or more JESD-compliant links in a multi-antenna base station, the BDFE has JESD transmitters (TXs) and receivers (RXs) that transmit and receive data to and from the RFIC chips and a time-based generator (TBGEN) that generates sync and idle signals that ensure that the processing of the different JESD TXs and RXs are aligned in time for data associated with a single logical group of antennas. The TBGEN has hardware-based alignment circuitry that generates the sync and idle signals, thereby avoiding the latency and unpredictability inherent with software-based solutions.

    Abstract translation: 对于在多天线基站中通过两个或多个JESD兼容链路上的一个或多个射频集成电路（RFIC）芯片进行通信的基带数字前端（BDFE）处理器，BDFE具有JESD发射机（TX） 以及向RFIC芯片发送数据和从RFIC芯片接收数据的接收器（RX）以及产生同步和空闲信号的基于时间的发生器（TBGEN），其确保不同JESD TX和RX的处理在时间上与数据相关联 具有单个逻辑组天线。 TBGEN具有基于硬件的对准电路，可生成同步和空闲信号，从而避免基于软件的解决方案固有的延迟和不可预测性。

    Scheduler for layer mapped code words
    6.
    发明授权
    Scheduler for layer mapped code words 有权

    公开(公告)号：US10045366B2

    公开(公告)日：2018-08-07

    申请号：US15213364

    申请日：2016-07-18

    Applicant: FREESCALE SEMICONDUCTOR, INC.

    Inventor： Somvir Dahiya ,  Arvind Kaushik ,  Aviel Livay ,  Amrit P. Singh

    IPC: H04W72/12 ,  H04L25/05

    Abstract: An eNode-B includes PUSH mapping hardware for improved performance. A scheduler schedules first and second code words of first and second respective user devices. A buffer receives and stores first and second identifiers. A de-multiplexer outputs a first code word number based on the first identifier and a second code word number based on the second identifier. A set of completion queues store the first and second code word numbers. A sequence controller generates first and second select signals corresponding to the first and second identifiers. A multiplexer outputs one of the first and second code word numbers based on the select signals, and the scheduler schedules the first and second code words based on the first and second identifiers.

    System for recovering unresponsive common public radio interface (CPRI) nodes
    8.
    发明授权
    System for recovering unresponsive common public radio interface (CPRI) nodes 有权
    用于恢复无响应的公共无线电接口（CPRI）节点的系统

    公开(公告)号：US09332567B1

    公开(公告)日：2016-05-03

    申请号：US14724738

    申请日：2015-05-28

    Applicant: FREESCALE SEMICONDUCTOR, INC.

    Inventor： Inayat Ali ,  Somvir Dahiya ,  Arvind Kaushik ,  Sachin Prakash

    IPC: H04B7/00 ,  H04W72/12 ,  H04W24/04

    CPC classification number: H04W24/04 ,  H04W88/02

    Abstract: An integrated circuit (IC) in an unresponsive radio equipment (RE) node includes a common public radio interface (CPRI) controller, a processor, and a system reset controller that includes an L1 (Layer 1) reset controller. The CPRI controller generates a reset request signal based on a CPRI reset request received from an RE controller (REC). The L1 reset controller generates a traffic stop signal based on the reset request signal. The CPRI controller generates a traffic idle signal based on the traffic stop signal. The L1 reset controller receives the traffic idle signal before a predetermined time period and generates a system reset signal for resetting the processor, thereby recovering the unresponsive RE node without disrupting the network topology of a communication system that includes the REC and multiple RE nodes including the unresponsive RE node connected via a CPRI link.

    Abstract translation: 无响应无线电设备（RE）节点中的集成电路（IC）包括公共无线电接口（CPRI）控制器，处理器和包括L1（层1）复位控制器的系统复位控制器）。 CPRI控制器基于从RE控制器（REC）接收到的CPRI复位请求产生复位请求信号。 L1复位控制器基于复位请求信号产生交通停止信号。 CPRI控制器基于交通停止信号产生流量空闲信号。 L1复位控制器在预定时间段之前接收业务空闲信号，并产生用于重置处理器的系统复位信号，从而恢复无响应的RE节点，而不会中断包括REC和包括REC的多个RE节点的通信系统的网络拓扑 无响应的RE节点通过CPRI链路连接。

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