公开(公告)号：US09332567B1

公开(公告)日：2016-05-03

申请号：US14724738

申请日：2015-05-28

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Inayat Ali ,  Somvir Dahiya ,  Arvind Kaushik ,  Sachin Prakash

IPC: H04B7/00 ,  H04W72/12 ,  H04W24/04

CPC classification number: H04W24/04 ,  H04W88/02

Abstract: An integrated circuit (IC) in an unresponsive radio equipment (RE) node includes a common public radio interface (CPRI) controller, a processor, and a system reset controller that includes an L1 (Layer 1) reset controller. The CPRI controller generates a reset request signal based on a CPRI reset request received from an RE controller (REC). The L1 reset controller generates a traffic stop signal based on the reset request signal. The CPRI controller generates a traffic idle signal based on the traffic stop signal. The L1 reset controller receives the traffic idle signal before a predetermined time period and generates a system reset signal for resetting the processor, thereby recovering the unresponsive RE node without disrupting the network topology of a communication system that includes the REC and multiple RE nodes including the unresponsive RE node connected via a CPRI link.

Abstract translation: 无响应无线电设备（RE）节点中的集成电路（IC）包括公共无线电接口（CPRI）控制器，处理器和包括L1（层1）复位控制器的系统复位控制器）。 CPRI控制器基于从RE控制器（REC）接收到的CPRI复位请求产生复位请求信号。 L1复位控制器基于复位请求信号产生交通停止信号。 CPRI控制器基于交通停止信号产生流量空闲信号。 L1复位控制器在预定时间段之前接收业务空闲信号，并产生用于重置处理器的系统复位信号，从而恢复无响应的RE节点，而不会中断包括REC和包括REC的多个RE节点的通信系统的网络拓扑 无响应的RE节点通过CPRI链路连接。

公开(公告)号：US09407264B1

公开(公告)日：2016-08-02

申请号：US14714333

申请日：2015-05-17

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Inayat Ali ,  Parul Sharma

IPC: H03K19/0175 ,  H03K19/00

CPC classification number: H03K19/0016

Abstract: A system for isolating a first power domain from a second power domain in an integrated circuit includes receiving an input signal from the first power domain and receiving a set of bits from a programmable register. An isolation enable signal indicative of isolating the first power domain from the second power domain is generated, and an intermediate signal based on the isolation enable signal and the input signal is generated. At least one of the input signal, a logic low signal, a logic high signal, and the intermediate signal is output based on the isolation enable signal and the set of bits.

Abstract translation: 用于将第一功率域与集成电路中的第二功率域隔离的系统包括从第一功率域接收输入信号并从可编程寄存器接收一组位。 产生指示将第一功率域与第二功率域隔离的隔离使能信号，并且产生基于隔离使能信号和输入信号的中间信号。 输入信号，逻辑低电平信号，逻辑高电平信号和中间信号中的至少一个基于隔离使能信号和位组输出。