公开(公告)号：US20160343809A1

公开(公告)日：2016-11-24

申请号：US14719999

申请日：2015-05-22

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： BRUCE M. GREEN ,  JENN HWA HUANG ,  VIKAS S. SHILIMKAR

IPC: H01L29/20 ,  H01L29/06 ,  H01L29/205 ,  H01L23/522 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L23/66 ,  H01L29/778

CPC classification number: H01L29/2003 ,  H01L21/30621 ,  H01L21/76224 ,  H01L23/481 ,  H01L23/5227 ,  H01L23/66 ,  H01L28/10 ,  H01L29/0657 ,  H01L29/4175 ,  H01L29/66462 ,  H01L29/7787 ,  H01L2223/6605

Abstract: An embodiment of a device includes a semiconductor substrate, a transistor formed at the first substrate surface, a first conductive feature formed over the first substrate surface and electrically coupled to the transistor, and a second conductive feature covering only a portion of the second substrate surface to define a first conductor-less region. A cavity vertically aligned with the first conductive feature within the first conductor-less region extends into the semiconductor substrate. A dielectric medium may be disposed within the cavity and have a dielectric constant less than a dielectric constant of the semiconductor substrate. A method for forming the device may include forming a semiconductor substrate, forming a transistor on the semiconductor substrate, forming the first conductive feature, forming the second conductive feature, forming the conductor-less region, forming the cavity, and filling the cavity with the dielectric medium.

Abstract translation: 器件的实施例包括半导体衬底，形成在第一衬底表面处的晶体管，形成在第一衬底表面上并电耦合到晶体管的第一导电特征，以及仅覆盖第二衬底表面的一部分的第二导电特征 以限定第一无导体区域。 在第一无导体区域内与第一导电特征垂直对准的空腔延伸到半导体衬底中。 电介质可以设置在空腔内并具有小于半导体衬底的介电常数的介电常数。 用于形成器件的方法可以包括形成半导体衬底，在半导体衬底上形成晶体管，形成第一导电特征，形成第二导电特征，形成无导体区域，形成腔体，以及填充腔体 电介质。