公开(公告)号：US20240204091A1

公开(公告)日：2024-06-20

申请号：US18084438

申请日：2022-12-19

申请人： Intel Corporation

发明人： Heli Vora ,  Marko Radosavljevic ,  Pratik Koirala ,  Han Wui Then ,  Michael Beumer ,  Ahmad Zubair ,  Samuel Bader

IPC分类号： H01L29/778 ,  H01L21/285 ,  H01L21/306 ,  H01L29/20 ,  H01L29/47 ,  H01L29/66

CPC分类号： H01L29/7786 ,  H01L21/28581 ,  H01L21/30621 ,  H01L29/2003 ,  H01L29/475 ,  H01L29/66462

摘要： Devices, transistor structures, systems, and techniques are described herein related to low aluminum concentration aluminum gallium nitride interlayers for group III-nitride enhancement mode transistors. The low aluminum concentration aluminum gallium nitride interlayer includes a lower aluminum concentration than a polarization layer of the transistor, such that the polarization layer induces a two-dimensional electron gas in a semiconductor layer of the transistor. The low aluminum concentration aluminum gallium nitride interlayer may be implemented as an etch stop layer, as a gate liner, or both.

公开(公告)号：US11987879B2

公开(公告)日：2024-05-21

申请号：US17673667

申请日：2022-02-16

申请人： Applied Materials, Inc.

发明人： Armin Saeedi Vahdat ,  Yan Zhang ,  John Hautala

IPC分类号： H01L21/306 ,  C23C14/48 ,  C23C16/30 ,  C23C16/40 ,  C23C16/513 ,  C23C28/04 ,  H01L21/3065

CPC分类号： C23C16/303 ,  C23C14/48 ,  C23C16/40 ,  C23C16/513 ,  C23C28/04 ,  H01L21/30604 ,  H01L21/30621 ,  H01L21/3065

摘要： Disclosed are approaches for forming semiconductor device cavities. One method may include providing a set of semiconductor structures defining an opening, wherein the opening has a first opening width along an upper portion of the opening and a second opening width along a lower portion of the opening, the first opening width being greater than the second opening width. The method may further include forming a blocking layer along the set of semiconductor structures by delivering a material at a non-zero angle of inclination relative to a normal extending perpendicular from a top surface of the set of semiconductor structures. The blocking layer may be formed along the upper portion of the opening without being formed along the lower portion of the opening, and wherein an opening through the blocking layer is present above the opening.

公开(公告)号：US11916130B2

公开(公告)日：2024-02-27

申请号：US17186533

申请日：2021-02-26

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kuen-Ting Shiu ,  Tak H. Ning ,  Jeng-Bang Yau ,  Cheng-Wei Cheng ,  Ko-Tao Lee

IPC分类号： H01L29/66 ,  H01L29/737 ,  H01L21/308 ,  H01L29/06 ,  H01L21/306 ,  H01L29/205

CPC分类号： H01L29/66318 ,  H01L21/308 ,  H01L21/30621 ,  H01L29/0649 ,  H01L29/205 ,  H01L29/737

摘要： A lateral bipolar junction transistor including an emitter region, base region and collector region laterally orientated over a type IV semiconductor substrate, each of the emitter region, the base region and the collector region being composed of a type III-V semiconductor material. A buried oxide layer is present between the type IV semiconductor substrate and the emitter region, the base region and the collector region. The buried oxide layer having a pedestal aligned with the base region.

公开(公告)号：US20230170221A1

公开(公告)日：2023-06-01

申请号：US18056169

申请日：2022-11-16

申请人： ASM IP Holding, B.V.

发明人： Charles Dezelah ,  Viljami Pore ,  Varun Sharma

IPC分类号： H01L21/306

CPC分类号： H01L21/30621

摘要： The current disclosure relates to a method of etching etchable material from a semiconductor substrate is disclosed. Th method comprises providing a substrate comprising the etchable material into a reaction chamber and providing a haloalkylamine into the reaction chamber in vapor phase for etching the etchable material. The disclosure further relates to a semiconductor processing assembly, and to a method of cleaning a reaction chamber.

公开(公告)号：US20190252202A1

公开(公告)日：2019-08-15

申请号：US16082672

申请日：2017-03-16

申请人： ZEON CORPORATION

发明人： Takaaki SAKURAI

IPC分类号： H01L21/311

CPC分类号： H01L21/31116 ,  H01L21/30621 ,  H01L21/3065 ,  H01L21/31053 ,  H01L21/31105

摘要： A plasma etching method according to the present disclosure includes a first etching step of performing plasma etching of the silicon nitride film on the workpiece by supplying a processing gas containing a gas of a compound represented by a composition formula C3H2BrF3 including a 2-bromo-3,3,3-trifluoropropene gas, a (Z)-1-bromo-3,3,3-trifluoropropene gas, an (E)-1-bromo-3,3,3-trifluoropropene gas, and/or a 3-bromo-2,3,3-trifluoropropene gas into the processing chamber, such that a ratio CF2/F obtained by emission spectrometry of the gas of the compound represented by the composition formula C3H2BrF3 is at least 0.33 within the processing chamber.

公开(公告)号：US20190207020A1

公开(公告)日：2019-07-04

申请号：US15857347

申请日：2017-12-28

申请人： Vanguard International Semiconductor Corporation

发明人： Hsin-Chih LIN ,  Yu-Chieh CHOU

IPC分类号： H01L29/778 ,  H01L29/78 ,  H01L29/205 ,  H01L29/20 ,  H01L21/02 ,  H01L29/66

CPC分类号： H01L29/7787 ,  H01L21/02271 ,  H01L21/0254 ,  H01L21/30621 ,  H01L21/3081 ,  H01L21/3086 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7851

摘要： A semiconductor device is provided. The semiconductor device includes a substrate and a first III-V group compound semiconductor layer disposed on the substrate. The first III-V group compound semiconductor layer includes a fin structure having a top surface, a first sidewall, and a second sidewall opposite to the first sidewall. The semiconductor device also includes a second III-V group compound semiconductor layer disposed on the first III-V group compound semiconductor layer. The first III-V group compound semiconductor layer and the second III-V group compound semiconductor layer are made of different materials. The semiconductor device also includes a gate electrode disposed on the second III-V group compound semiconductor layer.

公开(公告)号：US20190198655A1

公开(公告)日：2019-06-27

申请号：US16021984

申请日：2018-06-28

申请人： Kabushiki Kaisha Toshiba ,  Toshiba Infrastructure Systems & Solutions Corporation

发明人： Keiichi MATSUSHITA

IPC分类号： H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L23/31 ,  H01L21/02 ,  H01L21/306 ,  H01L21/24 ,  H01L29/66

CPC分类号： H01L29/7787 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/246 ,  H01L21/30621 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41766 ,  H01L29/66462

摘要： A semiconductor device includes a substrate: a first nitride semiconductor layer formed on the substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and containing a gallium element; a source electrode and a drain electrode formed on the second nitride semiconductor layer and contacting the second nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer and containing an indium element and an aluminum element; and a gate electrode formed on the third nitride semiconductor layer and formed between the source electrode and the drain electrode.

公开(公告)号：US20190198384A1

公开(公告)日：2019-06-27

申请号：US15852372

申请日：2017-12-22

申请人： Vanguard International Semiconductor Corporation

发明人： Hsin-Chih LIN ,  Shin-Cheng LIN ,  Yung-Hao LIN

IPC分类号： H01L21/762 ,  H01L29/20 ,  H01L29/205 ,  H01L29/06 ,  H01L29/778 ,  H01L21/265 ,  H01L21/306 ,  H01L29/66

CPC分类号： H01L21/76237 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/2654 ,  H01L21/30621 ,  H01L29/0653 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7787

摘要： A method for forming a semiconductor device is provided. A substrate is provided. An epitaxial layer is formed on the substrate. An insulation region and an active region are defined on the upper surface of the epitaxial layer. An insulation structure is formed within the insulation region by an ion implantation process and an etching process, wherein the insulation structure includes a first insulation structure and a second insulation structure. A gate is formed on the epitaxial layer and is disposed within the active region. A source and a drain are formed on opposite sides of the gate and within the active region. A semiconductor device is also provided.

公开(公告)号：US20180182882A1

公开(公告)日：2018-06-28

申请号：US15796715

申请日：2017-10-27

申请人： SixPoint Materials, Inc.

发明人： Tadao Hashimoto ,  Daisuke Ueda

IPC分类号： H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/32 ,  H01L29/36 ,  H01L29/45 ,  H01L21/02 ,  H01L21/306 ,  H01L21/285 ,  H01L29/66 ,  C30B29/40 ,  C30B7/10 ,  C30B25/20

CPC分类号： H01L29/7371 ,  C30B7/105 ,  C30B25/20 ,  C30B29/406 ,  H01L21/02008 ,  H01L21/02389 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02634 ,  H01L21/02639 ,  H01L21/28575 ,  H01L21/30621 ,  H01L21/3065 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/32 ,  H01L29/36 ,  H01L29/42304 ,  H01L29/452 ,  H01L29/66204 ,  H01L29/66219 ,  H01L29/66318 ,  H01L29/66356 ,  H01L29/66462 ,  H01L29/66924 ,  H01L29/732 ,  H01L29/7391 ,  H01L29/7787 ,  H01L29/7788 ,  H01L29/8083 ,  H01L29/8611

摘要： The present invention discloses an electronic device formed of a group III nitride. In one embodiment, a substrate is fabricated by the ammonothermal method and a drift layer is fabricated by hydride vapor phase epitaxy. After etching a trench, p-type contact pads are made by pulsed laser deposition followed by n-type contact pads by pulsed laser deposition. The bandgap of the p-type contact pad is designed larger than that of the drift layer. Upon forward bias between p-type contact pads (gate) and n-type contact pads (source), holes and electrons are injected into the drift layer from the p-type contact pads and n-type contact pads. Injected electrons drift to the backside of the substrate (drain).

公开(公告)号：US20180182873A1

公开(公告)日：2018-06-28

申请号：US15796708

申请日：2017-10-27

申请人： SixPoint Materials, Inc.

发明人： Tadao Hashimoto ,  Daisuke Ueda

IPC分类号： H01L29/739 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/10 ,  C30B7/10 ,  C30B25/20 ,  C30B29/40

CPC分类号： H01L29/7371 ,  C30B7/105 ,  C30B25/20 ,  C30B29/406 ,  H01L21/02389 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02634 ,  H01L21/02639 ,  H01L21/28575 ,  H01L21/30621 ,  H01L21/3065 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/32 ,  H01L29/36 ,  H01L29/42304 ,  H01L29/452 ,  H01L29/66204 ,  H01L29/66219 ,  H01L29/66318 ,  H01L29/66356 ,  H01L29/66462 ,  H01L29/66924 ,  H01L29/7391 ,  H01L29/7787 ,  H01L29/7788 ,  H01L29/8083 ,  H01L29/8611

摘要： The present invention discloses an electronic device formed of a group III nitride. In one embodiment, a substrate is fabricated by the ammonothermal method and a drift layer is fabricated by hydride vapor phase epitaxy. After etching a trench, p-type contact pads are made by pulsed laser deposition followed by n-type contact pads by pulsed laser deposition. The bandgap of the p-type contact pad is designed larger than that of the drift layer. Upon forward bias between p-type contact pads (gate) and n-type contact pads (source), holes and electrons are injected into the drift layer from the p-type contact pads and n-type contact pads. Injected electrons drift to the backside of the substrate (drain).