Versatile serial concatenated convolutional codes
    1.
    发明授权
    Versatile serial concatenated convolutional codes 有权
    通用串行级联卷积码

    公开(公告)号:US06785861B2

    公开(公告)日:2004-08-31

    申请号:US09781130

    申请日:2001-02-09

    IPC分类号: H03M1300

    摘要: An input digital signal is encoded by subjecting it to a first convolutional coding step followed by an interleaving step and a second convolutional coding step. The serial concatenated convolutional coded signal thus obtained is then subjected to modulation by means of a two-dimensional modulation scheme such as M-PSK or M-QAM. The corresponding decoding process involves an iterative decoding algorithm based on cascaded logarithmic soft-input soft-output processing steps.

    摘要翻译: 通过对输入数字信号进行经过交织步骤和第二卷积编码步骤的第一卷积编码步骤进行编码。 然后通过诸如M-PSK或M-QAM的二维调制方案对如此获得的串行级联卷积编码信号进行调制。 相应的解码过程涉及基于级联对数软输入软输出处理步骤的迭代解码算法。

    Prunable S-random block interleaver method and corresponding interleaver
    2.
    发明授权
    Prunable S-random block interleaver method and corresponding interleaver 有权
    可修复的S随机块交织器方法和相应的交织器

    公开(公告)号:US07210075B2

    公开(公告)日:2007-04-24

    申请号:US10143531

    申请日:2002-05-09

    IPC分类号: G06F11/00

    摘要: A method for designing a new prunable S-random interleaver class to be used as a constituent part of turbo codes. With respect to previously proposed solutions the method has the advantage of being prunable to different block sizes while exhibiting at the same time, for any considered block size, performance comparable with the optimized “ad hoc” S-random interleavers. Another advantage is that, as for every S-random interleaver, the design rules are independent of the constituent codes and of the puncturing rate applied to the turbo code. Therefore, these interleavers potentially can find applications in any turbo code scheme that requires interleaver size flexibility and code rate versatility, thanks to the advantage of requiring a single law storage (i e., one ROM storage instead of several ROMs) from which all the others are obtained by pruning, without compromising the overall error rate performance.

    摘要翻译: 一种用于设计新的可修剪的S随机交织器类的方法,以用作turbo码的组成部分。 对于先前提出的解决方案,该方法的优点是可以同时展现不同的块大小,对于任何考虑的块大小,与优化的“ad hoc”S随机交织器相当的性能。 另一个优点是,对于每个S随机交织器,设计规则独立于构成码和应用于turbo码的打孔率。 因此,这些交织器潜在地可以在需要交织器大小灵活性和代码率多功能性的任何turbo码方案中找到应用,这得益于需要单一定律存储(即,一个ROM存储而不是几个ROM)​​的优点, 其他人通过修剪获得,而不会影响整体错误率性能。

    Video images decoder architecture for implementing a 40 MS processing
algorithm in high definition television
    3.
    发明授权
    Video images decoder architecture for implementing a 40 MS processing algorithm in high definition television 失效
    用于在高分辨率电视中实现40MS处理算法的视频图像解码器架构

    公开(公告)号:US5459519A

    公开(公告)日:1995-10-17

    申请号:US241604

    申请日:1994-05-11

    IPC分类号: H04N7/015 H04N7/01

    CPC分类号: H04N7/0155

    摘要: A video image decoder architecture for implementing a processing algorithm in the 40-ms mode on high-resolution TV sets, of a kind adapted to handle TV signals being received on respective transmission channels (J,L), which comprises a video signal demultiplexer receiving the transmission channels (J,L); and respective processing blocks for separately handling the signals from each of the channels (J,L). Each processing block includes a video image format converter, a local memory connected to an output of the converter, and at least one median filter and one systolic filter cascade connected after the memory for restoring, by interpolation, signal samples related to successive lines of the video image. A summing node adds the outputs from each processing block so as to obtain a time mean between restored samples of the channels (J,L). This architecture drastically reduces the number of memories required for processing the restored algorithm, as well as reducing overall silicon area requirements for the system. Accordingly, the whole 40-millisecond processing portion may be integrated into a single chip.

    摘要翻译: 一种用于在高分辨率电视机上实现40ms模式的处理算法的视频图像解码器架构,其适用于处理在各个传输信道(J,L)上接收的TV信号,其包括视频信号解复用器接收 传输通道(J,L); 以及用于分别处理来自每个通道(J,L)的信号的各个处理块。 每个处理块包括视频图像格式转换器,连接到转换器的输出的本地存储器,以及连接在存储器之后的至少一个中值滤波器和一个收缩滤波器级联,用于通过内插来恢复与相关行的相关行相关的信号样本 视频图像。 求和节点将来自每个处理块的输出相加以获得恢复的信道样本(J,L)之间的时间平均值。 这种架构大大减少了处理恢复的算法所需的存储器数量,并减少了系统的整体硅面积要求。 因此,整个40毫秒处理部分可以集成到单个芯片中。

    Method for reducing echoes in television equalizer video signals and
apparatus therefor
    4.
    发明授权
    Method for reducing echoes in television equalizer video signals and apparatus therefor 失效
    用于减少电视均衡器视频信号中的回波的方法及其装置

    公开(公告)号:US5512959A

    公开(公告)日:1996-04-30

    申请号:US255436

    申请日:1994-06-08

    IPC分类号: H04B7/015 H04N5/21

    CPC分类号: H04N5/211

    摘要: An adaptive method for suppressing video signal echoes in television equalizers including digital filters having coefficients which are updated in an adaptive and iterative manner using a modified LMS (Least Mean Square) algorithm until the difference, or output error, between a target output signal, called the reference signal, and an outgoing signal from the equalizer is gradually reduced. The method includes the steps of:--applying a "combing" technique to an original filter having K*N coefficients in order to select K comb filters having N coefficients each;--applying said LMS algorithm, with a variable convergence factor to each individual comb filter for a predetermined number of iterations;--gathering the resultant configurations of the comb filter coefficients and selecting a subfilter with N largest modulo coefficients therefrom;--updating the values of said N coefficients again by reiterating the LMS algorithm with variable convergence factor to said subfilter for a limited number of iterations;--clearing all the coefficients with a lower modulo value than a predetermined threshold value;--selecting a group of F coefficients by a slotting operation across those of said coefficients which have a cluster value: and--updating the value of said group of F coefficients, by reiterating the LMS algorithm with variable convergence factor, until the output error becomes smaller than a predetermined value.

    摘要翻译: 一种用于抑制电视均衡器中的视频信号回波的自适应方法,其包括具有使用修正的LMS(最小均方根)算法以自适应和迭代方式更新的系数的数字滤波器,直到目标输出信号 参考信号和来自均衡器的输出信号逐渐减小。 该方法包括以下步骤:将“梳理”技术应用于具有K * N个系数的原始滤波器,以便选择每个具有N个系数的K个梳状滤波器; 将具有可变收敛因子的所述LMS算法应用于每个单独梳状滤波器以进行预定次数的迭代; - 梳状滤波器系数的结果配置,并从中选择具有N个最大模数系数的子滤波器; 通过在有限数量的迭代中重复具有可变收敛因子的LMS算法来再次对所述N个系数的值进行重新设置; - 清除具有比预定阈值低的模数值的所有系数; 通过对具有簇值的所述系数的开槽操作选择一组F系数,并且通过重复具有可变收敛因子的LMS算法来更新所述F系数组的值,直到输出误差变小 超过预定值。