公开(公告)号：US20070177042A1

公开(公告)日：2007-08-02

申请号：US11344456

申请日：2006-01-30

申请人： Fan He ,  Carl Shurboff

发明人： Fan He ,  Carl Shurboff

IPC分类号： H04N5/335

CPC分类号： H04N5/37452

摘要： A circuit for use in an image sensor as well as an image sensing system using the circuit are set forth. The circuit comprises a memory device having a non-volatile memory cell, a control gate, a drain and a source. The circuit also employs a photosensitive semiconductor device that is positioned for exposure to electromagnetic radiation from an image. A pixel control circuit is connected to these components to direct the memory device and the photosensitive semiconductor device to a plurality of controlled modes. The controlled modes may include an erase mode and an exposure mode. In the erase mode, at least a portion of an electric charge is removed from the non-volatile memory cell to place the memory device in an initialized state. In the exposure mode, the non-volatile memory cell is charged at least partially in response to a voltage at a terminal of the photosensitive semiconductor device. The voltage at the terminal of the photosensitive semiconductor device corresponds to exposure of the photosensitive semiconductor device to the electromagnetic radiation from the image. The pixel control circuit may also direct the memory device and the photosensitive semiconductor device to further modes including a read mode and a data retention mode. In the read mode, current flow between the source and drain of the memory device is detected as an indicator of the charge on the non-volatile memory cell. In the data retention mode, the charge on the non-volatile memory cell of the memory device that was acquired during the exposure mode is maintained notwithstanding further exposure of the photosensitive semiconductor device to the electromagnetic radiation from the image. The circuit, and one or more peripheral support circuits, may be implemented in a monolithic substrate using, for example, conventional CMOS manufacturing processes.

摘要翻译： 阐述了一种用于图像传感器的电路以及使用该电路的图像感测系统。 电路包括具有非易失性存储单元，控制栅极，漏极和源极的存储器件。 该电路还采用光敏半导体器件，其定位用于暴露于来自图像的电磁辐射。 像素控制电路连接到这些组件以将存储器件和光敏半导体器件引导到多个受控模式。 受控模式可以包括擦除模式和曝光模式。 在擦除模式中，将电荷的至少一部分从非易失性存储单元移除，以将存储器件置于初始化状态。 在曝光模式下，响应于光敏半导体器件的端子处的电压，至少部分地对非易失性存储单元进行充电。 光敏半导体器件的端子处的电压对应于光敏半导体器件对来自图像的电磁辐射的曝光。 像素控制电路还可以将存储器件和光敏半导体器件引导到包括读取模式和数据保持模式的进一步模式。 在读取模式下，存储器件的源极和漏极之间的电流流动被检测为非易失性存储单元上的电荷的指示。 在数据保持模式下，尽管感光半导体器件进一步暴露于来自图像的电磁辐射，仍然维持在曝光模式期间获取的存储器件的非易失性存储单元上的电荷。 电路和一个或多个外围支持电路可以使用例如常规CMOS制造工艺在单片基板中实现。

公开(公告)号：US20070152133A1

公开(公告)日：2007-07-05

申请号：US11323097

申请日：2005-12-30

申请人： Fan He ,  Carl Shurboff

发明人： Fan He ,  Carl Shurboff

IPC分类号： H01L27/00

CPC分类号： H01L27/14643 ,  H01L27/14601 ,  H04N5/3745

摘要： A light sensing circuit (400) and image sensor array includes at least one light sensing element (402), such as a photodiode, and at least one ferroelectric element (404), such as a CMOS ferroelectric gate field effect transistor (FET), that is operatively coupled to the light sensing element to form a photo cell. The ferroelectric element provides charge storage as a non-volatile analog memory element. As such, a type of photo cell serves as a ferroelectric memory that can store the charge from the light sensing element and be programmed to provide electronic shutter operation.

摘要翻译： 光感测电路（400）和图像传感器阵列包括至少一个光敏元件（402），例如光电二极管，以及至少一个铁电元件（404），例如CMOS铁电栅极场效应晶体管（FET） 其可操作地耦合到光感测元件以形成光电池。 铁电元件作为非易失性模拟存储元件提供电荷存储。 因此，一种类型的光电池用作铁电存储器，其可以存储来自光感测元件的电荷并且被编程以提供电子快门操作。

公开(公告)号：US20060290798A1

公开(公告)日：2006-12-28

申请号：US11168945

申请日：2005-06-28

申请人： Fan He ,  Carl Shurboff

发明人： Fan He ,  Carl Shurboff

IPC分类号： H04N5/335 ,  H04N3/14

CPC分类号： H04N5/37452 ,  G11C16/0408 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/14643 ,  H04N5/341

摘要： A circuit for use in an image sensor as well as an image sensing system using the circuit are set forth. The circuit comprises a floating gate semiconductor device having a floating gate, a control gate, a drain and a source. The circuit also employs a photosensitive semiconductor device that is positioned for exposure to electromagnetic radiation from an image. A pixel control circuit is connected to these components to direct the floating gate semiconductor device and the photosensitive semiconductor device to a plurality of controlled modes. The controlled modes may include an erase mode and an exposure mode. In the erase mode, at least a portion of an electric charge is removed from the floating gate to place the floating gate semiconductor device in an initialized state. In the exposure mode, the floating gate is charged at least partially in response to a voltage at a terminal of the photosensitive semiconductor device. The voltage at the terminal of the photosensitive semiconductor device corresponds to exposure of the photosensitive semiconductor device to the electromagnetic radiation from the image. The pixel control circuit may also direct the floating gate semiconductor device and the photosensitive semiconductor device to further modes including a read mode and a data retention mode. In the read mode, current flow between the source and drain of the floating gate semiconductor device is detected as an indicator of the charge on the floating gate. In the data retention mode, the charge on the floating gate of the floating gate semiconductor device that was acquired during the exposure mode is maintained notwithstanding further exposure of the photosensitive semiconductor device to the electromagnetic radiation from the image. The circuit, and one or more peripheral support circuits, may be implemented in a monolithic substrate using, for example, conventional CMOS manufacturing processes.

公开(公告)号：US20070046794A1

公开(公告)日：2007-03-01

申请号：US11215887

申请日：2005-08-30

申请人： Fan He ,  Michael Frenzer ,  Zili Li ,  Carl Shurboff

发明人： Fan He ,  Michael Frenzer ,  Zili Li ,  Carl Shurboff

IPC分类号： H04N9/04 ,  H04N3/14 ,  H04N5/335 ,  H04N9/083

CPC分类号： H04N9/045 ,  H04N5/3741 ,  H04N5/37452 ,  H04N5/376 ,  H04N2209/043

摘要： An apparatus (20) for recording a color image, comprises an image sensor (22) having a plurality of pixels (24) formed in a monolithic substrate. Each of the plurality of pixels (24) includes three floating gate semiconductor devices (80, 82, 84). A color tunable filter (30) is positioned between a photosensitive semiconductor device (86) and an electromagnetic radiation source. A FET transistor (130) has a drain (134) connected to the cathode (120) of the photodiode (86), and a source (136) connected to the anode (118) of the photodiode (86) and to control gates (94, 104, 114) of each of the three floating gate semiconductor devices (80, 82, 84). The color tunable filter (30) allows all desired combinations of colors to pass while each of the three floating gate semiconductor devices (80, 82, 84) are respectively selected to store the color image.

摘要翻译： 一种用于记录彩色图像的设备（20）包括具有形成在单片基板中的多个像素（24）的图像传感器（22）。 多个像素（24）中的每一个包括三个浮置栅极半导体器件（80,82,84）。 颜色可调滤光器（30）位于光敏半导体器件（86）和电磁辐射源之间。 FET晶体管（130）具有连接到光电二极管（86）的阴极（120）的漏极（134）和连接到光电二极管（86）的阳极（118）并且控制栅极（86）的源极 所述三个浮置栅极半导体器件（80,82,84）中的每一个的栅极（94,104,114）。 颜色可调滤光器（30）允许所有期望的颜色组合通过，同时分别选择三个浮置栅极半导体器件（80,82,84）中的每一个以存储彩色图像。

公开(公告)号：US5852316A

公开(公告)日：1998-12-22

申请号：US298721

申请日：1994-08-31

申请人： Charles E. Weitzel ,  Carl Shurboff

发明人： Charles E. Weitzel ,  Carl Shurboff

IPC分类号： H01L27/095 ,  H01L21/338 ,  H01L27/06 ,  H01L29/778 ,  H01L29/812 ,  H03F3/189 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/0605

摘要： A gallium arsenide amplifier (10) utilizes a P-channel heterojunction transistor (12) and an N-channel heterojunction transistor (11) connected in a stacked configuration. The gate width of the P-channel heterojunction transistor is scaled so that the transconductance of the P-channel heterojunction transistor approximately equals the transconductance of the N-channel heterojunction transistor. The gate length (44) of the N-channel heterojunction transistor is scaled so that the input impedance of the N-channel heterojunction transistor approximately equals the input impedance of the P-channel heterojunction transistor.

摘要翻译： 砷化镓放大器（10）利用以堆叠结构连接的P沟道异质结晶体管（12）和N沟道异质结晶体管（11）。 P沟道异质结晶体管的栅极宽度被缩放，使得P沟道异质结晶体管的跨导大致等于N沟道异质结晶体管的跨导。 N沟道异质结晶体管的栅极长度（44）被缩放，使得N沟道异质结晶体管的输入阻抗近似等于P沟道异质结晶体管的输入阻抗。