公开(公告)号：US20230253028A1

公开(公告)日：2023-08-10

申请号：US17667499

申请日：2022-02-08

Applicant: Faraday Technology Corp.

Inventor： Sridhar Cheruku ,  Sivaramakrishnan Subramanian ,  Hussainvali Shaik ,  Ko-Ching Chao

IPC: G11C11/4076

CPC classification number: G11C11/4076

Abstract: The present invention provides a physical layer and associated signal processing method for clock domain transfer of quarter-rate data. In the embodiments of the present invention, the quarter-rate data is processed by many sampling circuits by using a first clock signal, a second clock signal and a third clock signal, and phases of these clock signals are aligned by using a training mechanism to that the clock signals have better timing margins

公开(公告)号：US11935577B2

公开(公告)日：2024-03-19

申请号：US17667499

申请日：2022-02-08

Applicant: Faraday Technology Corp.

Inventor： Sridhar Cheruku ,  Sivaramakrishnan Subramanian ,  Hussainvali Shaik ,  Ko-Ching Chao

IPC: G11C7/22 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4096 ,  G11C7/1087

Abstract: The present invention provides a physical layer and associated signal processing method for clock domain transfer of quarter-rate data. In the embodiments of the present invention, the quarter-rate data is processed by many sampling circuits by using a first clock signal, a second clock signal and a third clock signal, and phases of these clock signals are aligned by using a training mechanism to that the clock signals have better timing margins.

公开(公告)号：US11005468B1

公开(公告)日：2021-05-11

申请号：US17016333

申请日：2020-09-09

Applicant: Faraday Technology Corp.

Inventor： Sivaramakrishnan Subramanian ,  Sridhar Cheruku ,  Sandeep Kumar Mohanta ,  Hussainvali Shaik

IPC: H03K5/156 ,  H03L7/081

Abstract: A method for performing duty-cycle correction of an output clock in a Double Data Rate (DDR) system includes: setting a fixed delay of a rising-edge of the output clock as a parameter X which is equal to a digital Master Delay Locked Loop (MDLL) code of the DDR system multiplied by a percentage representing an estimated distortion of the duty-cycle of the output clock from a desired duty-cycle; shifting the rising-edge of the output clock by the fixed delay; and determining whether a duty cycle of the shifted output clock meets the desired duty-cycle. When a duty-cycle of the shifted output clock meets the desired duty-cycle, the fixed rising-edge delay is taken as a final delay code for the output clock; otherwise, a falling-edge of the output clock is shifted by an amount in a range between 0 and NX, wherein N is an integer.