公开(公告)号：US20240072814A1

公开(公告)日：2024-02-29

申请号：US17893191

申请日：2022-08-23

Applicant: Faraday Technology Corp.

Inventor： VINOD KUMAR JAIN

IPC: H03L7/197 ,  H03L7/089 ,  H03L7/099

CPC classification number: H03L7/1976 ,  H03L7/0891 ,  H03L7/099

Abstract: A Phase Locked Loop (PLL) with reduced jitter includes: a phase detector, for comparing the phases of a reference clock and feedback clock to generate up and down control signals; a Voltage Controlled Oscillator (VCO) for generating an oscillation signal; an output divider, for dividing the oscillation signal to generate an output clock; a fractional feedback divider for receiving the oscillation signal and performing frequency division on the oscillation signal according to a modulated sequence to generate a modulated clock; and a divider coupled in series to the fractional feedback divider, for dividing the modulated clock of the fractional feedback divider by a fixed modulus to generate a divided clock. A frequency of the modulated clock of the fractional feedback divider is an integer multiple of the frequency of the divided clock, and one of the modulated clock and divided clock is used as the feedback clock.

公开(公告)号：US20230163740A1

公开(公告)日：2023-05-25

申请号：US17531811

申请日：2021-11-22

Applicant: Faraday Technology Corp.

Inventor： PRATEEK KUMAR GOYAL ,  RAGHU NANDAN CHEPURI ,  VINOD KUMAR JAIN

IPC: H03G3/30 ,  H04B10/69 ,  H03F3/45 ,  H03M1/12

CPC classification number: H03G3/3084 ,  H03F3/45 ,  H03M1/12 ,  H04B10/6933 ,  H03F2200/375 ,  H03F2203/45212

Abstract: A method for removing offset in a receiver of an integrated circuit (IC) includes: determining digital codes of differential input voltages of an amplifier in a first receiving lane of the receiver; comparing the digital codes to a digital code corresponding to an optimum common mode voltage (VCM) of the receiver; according to the comparison, determining a bias code for adjusting both the differential input voltages to match the optimum VCM; and inputting the bias code to a bias circuit of the receiver. The first receiving lane of the receiver includes a plurality of amplifiers. The method steps are repeated for each amplifier of the plurality of amplifiers, and then repeated for all receiving lanes of the IC.