公开(公告)号：US20080168410A1

公开(公告)日：2008-07-10

申请号：US11869717

申请日：2007-10-09

申请人： Fedor G. Pikus ,  Ellis Cohen

发明人： Fedor G. Pikus ,  Ellis Cohen

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

摘要： One or more properties can be associated with a design object in a microdevice design. The design object may be an object in a physical layout design for a microdevice, such as a geometric element in a layout design. The design object also may be a collection of geometric elements in a layout design, such as a net, a cell in a hierarchical design, or even a collection of all of the geometric elements in a layer of a design. Still further, the design object may even be an item in a logical circuit design, such as a net in a logical circuit design for an integrated circuit. The values of one or more properties may be statically assigned for or dynamically generated during a design process performed by an electronic design automation tool. A property may be assigned a constant value or a value defined by an equation or other type of script that includes one or more variables. A property may be simple, where the definition of the property's value is not dependent upon the value of any other properties. Alternately, a property may be a compound property, where the definition of the property's value incorporates another, previously-determined property value. Still further, a property may be an alternative property, where the property is assigned one value definition under a first set of conditions and assigned another value definition under a second set of conditions. A first electronic design automation process may generate one or more property values. The generated property values then can be passed to another electronic design automation process in the design analysis flow for its use.

公开(公告)号：US08751981B2

公开(公告)日：2014-06-10

申请号：US13532484

申请日：2012-06-25

申请人： Fedor G. Pikus ,  Kobi Kresh

发明人： Fedor G. Pikus ,  Kobi Kresh

IPC分类号： G06F9/45

CPC分类号： G06F17/5022 ,  G06F17/5081

摘要： A technique for reducing a circuit listing. According to examples of the technique, at least a portion of a circuit listing is analyzed to identify occurrences of a circuit structure made up of a plurality of circuit components. For each identified occurrence of the defined circuit structure, an injection data object is created corresponding to the plurality of components, and the injection data object is substituted into the portion of the circuit listing in place of the plurality of components. For each occurrence of the defined structure, one or more properties of the occurrence of the defined structure may be determined and contained by the corresponding injection data object.

摘要翻译： 一种减少电路列表的技术。 根据该技术的示例，分析电路列表的至少一部分以识别由多个电路部件组成的电路结构的出现。 对于定义的电路结构的每个识别的出现，对应于多个分量创建注入数据对象，并且将注入数据对象替换为电路列表的部分来代替多个分量。 对于定义结构的每次出现，可以由相应的注入数据对象确定并包含所定义结构的出现的一个或多个属性。

公开(公告)号：US07222312B2

公开(公告)日：2007-05-22

申请号：US10895485

申请日：2004-07-20

申请人： John G. Ferguson ,  Fedor G. Pikus ,  Kyohei Sakajiri ,  Laurence W. Grodd

发明人： John G. Ferguson ,  Fedor G. Pikus ,  Kyohei Sakajiri ,  Laurence W. Grodd

IPC分类号： G06F17/50 ,  G04Q99/00 ,  H04L9/00 ,  H04L9/3213

CPC分类号： G06Q40/04 ,  H04L9/0838 ,  H04L2209/16

摘要： Described herein are methods and systems for secure exchange of information related to electronic design automation. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information may be provided to an electronic design automation tool for processing without revealing at least some of the secured information. For instance, rule files related to integrated circuit manufacturability may be selectively annotated to indicate portions thereof deserving of protection. An encryption tool may be used to secure the information so indicated and generate a file comprising secured information related to electronic design automation. An electronic design automation tool may then unlock and use the secured information without revealing the same. For instance, the tool may be a physical verification tool capable of verifying whether any of the one or more integrated circuit layouts may violate one or more of the secured rules. An error report may be generated without revealing the secured rules.

摘要翻译： 这里描述了用于安全地交换与电子设计自动化相关的信息的方法和系统。 被视为敏感而其他值得保护的信息可以通过加密，混淆和其他安全措施等方法来保护。 可以将安全信息提供给电子设计自动化工具用于处理，而不暴露至少一些安全信息。 例如，可以选择性地注释与集成电路可制造性相关的规则文件，以指示其应得到保护的部分。 可以使用加密工具来保护所指示的信息，并生成包括与电子设计自动化有关的安全信息的文件。 然后，电子设计自动化工具可以解锁和使用安全信息，而不会泄露它们。 例如，该工具可以是能够验证一个或多个集成电路布局中的任一个是否可能违反一个或多个安全规则的物理验证工具。 可能会生成错误报告，而不会泄露安全规则。

公开(公告)号：US20130080985A1

公开(公告)日：2013-03-28

申请号：US13426595

申请日：2012-03-21

申请人： Fedor G. Pikus ,  Ziyang Lu ,  Patrick D. Gibson

发明人： Fedor G. Pikus ,  Ziyang Lu ,  Patrick D. Gibson

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： Techniques for efficiently determining whether an interconnect line has an impedance component value below a maximum specified value. A specified maximum impedance component value is used to limit the number of interconnect lines that are analyzed by a parasitic extraction analysis process. An analysis window is created based upon the characteristics of the interconnect lines and the specified maximum impedance component value. The size of the window corresponds to the minimum length of the interconnect line that would have the specified maximum impedance component value. Once the analysis window has been created, the interconnect lines are examined to determine if any of them reaches to (or beyond) the analysis window, whereby interconnect lines that exceed the specified maximum impedance component value can be identified. If there are any remaining interconnect lines that have not been determined to exceed the specified maximum impedance component value through the use of the analysis window, then the impedance component values of these remaining interconnect lines can be specifically determined using a parasitic extraction process.

摘要翻译： 用于有效地确定互连线是否具有低于最大规定值的阻抗分量值的技术。 使用指定的最大阻抗分量值来限制通过寄生提取分析过程分析的互连线的数量。 基于互连线的特性和指定的最大阻抗分量值创建分析窗口。 窗口的大小对应于具有指定的最大阻抗分量值的互连线的最小长度。 一旦创建了分析窗口，就检查互连线以确定它们中的任何一个是否到达（或超出）分析窗口，从而可以识别出超过规定的最大阻抗分量值的互连线。 如果通过使用分析窗口还没有确定剩余的互连线未被确定为超过规定的最大阻抗分量值，那么这些剩余互连线的阻抗分量值可以使用寄生提取处理来具体确定。

公开(公告)号：US08302039B2

公开(公告)日：2012-10-30

申请号：US12758640

申请日：2010-04-12

申请人： John G. Ferguson ,  Fedor G. Pikus ,  Kyohei Sakajiri ,  Laurence W. Grodd

发明人： John G. Ferguson ,  Fedor G. Pikus ,  Kyohei Sakajiri ,  Laurence W. Grodd

IPC分类号： G06F17/50 ,  G06F21/00 ,  G06F12/14 ,  H04L29/06

CPC分类号： G06Q40/04 ,  H04L9/0838 ,  H04L2209/16

摘要： Described herein are methods and systems for secure exchange of information related to electronic design automation. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information may be provided to an electronic design automation tool for processing without revealing at least some of the secured information. For instance, rule files related to integrated circuit manufacturability may be selectively annotated to indicate portions thereof deserving of protection. An encryption tool may be used to secure the information so indicated and generate a file comprising secured information related to electronic design automation. An electronic design automation tool may then unlock and use the secured information without revealing the same. For instance, the tool may be a physical verification tool capable of verifying whether any of the one or more integrated circuit layouts may violate one or more of the secured rules. An error report may be generated without revealing the secured rules.

摘要翻译： 这里描述了用于安全地交换与电子设计自动化相关的信息的方法和系统。 被视为敏感而其他值得保护的信息可以通过加密，混淆和其他安全措施等方法来保护。 可以将安全信息提供给电子设计自动化工具用于处理，而不暴露至少一些安全信息。 例如，可以选择性地注释与集成电路可制造性相关的规则文件，以指示其应得到保护的部分。 可以使用加密工具来保护所指示的信息，并生成包括与电子设计自动化有关的安全信息的文件。 然后，电子设计自动化工具可以解锁和使用安全信息，而不会泄露它们。 例如，该工具可以是能够验证一个或多个集成电路布局中的任一个是否可能违反一个或多个安全规则的物理验证工具。 可能会生成错误报告，而不会泄露安全规则。

公开(公告)号：US20110145770A1

公开(公告)日：2011-06-16

申请号：US12780821

申请日：2010-05-14

申请人： Phillip A. Brooks ,  Fedor G. Pikus

发明人： Phillip A. Brooks ,  Fedor G. Pikus

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： An electronic design automation process, such as a layout-verses-schematic analysis process, may recognize a representation of a device from physical layout design data. Information, such as geometric information separately obtained from the physical layout design data, is then associated with the recognized device representation. The associated information can subsequently be used in a later electronic design automation operation involving the recognized device representation.

摘要翻译： 电子设计自动化过程（例如布局分析过程）可以从物理布局设计数据识别设备的表示。 然后将诸如从物理布局设计数据获得的几何信息的信息与识别的设备表示相关联。 相关信息可以随后用于涉及识别的设备表示的后来的电子设计自动化操作。

公开(公告)号：US20080148348A1

公开(公告)日：2008-06-19

申请号：US12036816

申请日：2008-02-25

申请人： John G. Ferguson ,  Fedor G. Pikus ,  Kyohei Sakajiri ,  Laurence W. Grodd

发明人： John G. Ferguson ,  Fedor G. Pikus ,  Kyohei Sakajiri ,  Laurence W. Grodd

IPC分类号： G06F21/00 ,  G06F21/24

CPC分类号： G06F21/6209 ,  G06F2221/2137

摘要： Information related to electronic design automation may be exchanged in a secure manner. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information may be processed without revealing at least some of the secured information. For instance, rule files related to integrated circuit manufacturability may be selectively annotated to indicate portions thereof deserving of protection. An encryption tool may be used to secure the information related to electronic design automation. An electronic design automation tool may then unlock and use the secured information without revealing the same. In one aspect, such access or secure use of the information may depend on one or more conditions being met (e.g., a time period or a number of uses or accesses). For instance, the tool may be a physical verification tool capable of verifying whether any of the one or more integrated circuit layouts may violate one or more of the secured rules.

摘要翻译： 与电子设计自动化相关的信息可以以安全的方式交换。 被视为敏感而其他值得保护的信息可以通过加密，混淆和其他安全措施等方法来保护。 可以处理安全信息，而不泄露至少一些安全信息。 例如，可以选择性地注释与集成电路可制造性相关的规则文件，以指示其应得到保护的部分。 可以使用加密工具来保护与电子设计自动化有关的信息。 然后，电子设计自动化工具可以解锁和使用安全信息，而不会泄露它们。 在一个方面，信息的这种访问或安全使用可以取决于满足的一个或多个条件（例如，一个时间段或多个使用或访问）。 例如，该工具可以是能够验证一个或多个集成电路布局中的任一个是否可能违反一个或多个安全规则的物理验证工具。

公开(公告)号：US09507902B2

公开(公告)日：2016-11-29

申请号：US13093828

申请日：2011-04-25

申请人： Eugene Anikin ,  Fedor G. Pikus ,  Laurence W. Grodd ,  David A. Abercrombie ,  John W. Stedman

发明人： Eugene Anikin ,  Fedor G. Pikus ,  Laurence W. Grodd ,  David A. Abercrombie ,  John W. Stedman

IPC分类号： G06F17/50 ,  G03F1/44 ,  H01L27/02

摘要： Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient. Additionally, some implementations may allow a user to simultaneously optimize the density of multiple layers of a circuit by adding fill polygons to multiple layers of a circuit design simultaneously. Representations of sections of a multilayer fill structure will then be added to corresponding layers the circuit design until a specified target density is met.

公开(公告)号：US08612919B2

公开(公告)日：2013-12-17

申请号：US11986564

申请日：2007-11-20

申请人： Fedor G. Pikus ,  David A. Abercrombie

发明人： Fedor G. Pikus ,  David A. Abercrombie

IPC分类号： G06F17/50 ,  G06F11/22

CPC分类号： G06F17/5081

摘要： An analog design-rule-check tool analyzes a microdevice design, such as an integrated circuit design, to identify occurrences of geometric elements that share a specified relationship. When the tool identifies such an occurrence of these geometric elements, it will associate or “cluster” these geometric elements together into an identifiable unit. For specified “clusters” of geometric elements, the analog design-rule-check tool will then determine the value of a measurement or measurements required by a user. Once the analog design-rule-check tool has determined the necessary measurement values, it will use those values to evaluate the function describing a model.

摘要翻译： 模拟设计规则检查工具分析微设计设计，例如集成电路设计，以识别共享指定关系的几何元素的出现。 当工具识别这些几何元素的这种出现时，它将将这些几何元素相关联或“聚集”到一个可识别的单元中。 对于几何元素的特定“簇”，模拟设计规则检查工具将确定用户所需的测量值或测量值。 一旦模拟设计规则检查工具确定了必要的测量值，它将使用这些值来评估描述模型的功能。

公开(公告)号：US20130198703A1

公开(公告)日：2013-08-01

申请号：US13592304

申请日：2012-08-22

申请人： Ziyang Lu ,  Fedor G. Pikus ,  Phillip A. Brooks

发明人： Ziyang Lu ,  Fedor G. Pikus ,  Phillip A. Brooks

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： Configuration templates reflect configuration information described in hierarchical circuit design data. The object configure information will include both template generic configuration information and instance specific configuration information. The template generic configuration information is configuration information that is common to all instantiations of a corresponding cell in the hierarchical circuit design data. The instance specific configuration information is then configuration information that is particular to one or more specific instantiations of the corresponding cell in the hierarchical circuit design data. After the object configuration templates have been generated, a configuration information analysis unit uses the object configuration information contained in the object configuration templates to identify objects having configuration data that match defined configuration criteria.

摘要翻译： 配置模板反映了分层电路设计数据中描述的配置信息。 对象配置信息将包括模板通用配置信息和实例特定配置信息。 模板通用配置信息是分层电路设计数据中对应单元的所有实例的公共配置信息。 然后，实例特定配置信息是分层电路设计数据中相应小区的一个或多个特定实例的特定配置信息。 在生成对象配置模板之后，配置信息分析单元使用包含在对象配置模板中的对象配置信息来识别具有与定义的配置准则相匹配的配置数据的对象。