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公开(公告)号：US07468763B2
公开(公告)日：2008-12-23
申请号：US11199661
申请日：2005-08-09
申请人： Feng Ying , Karl Hertzian Renner , Weider Peter Chang , Shereef Shehata , Viet Dinh , Xiaodong Wu , Walter Heinrich Demmer
发明人： Feng Ying , Karl Hertzian Renner , Weider Peter Chang , Shereef Shehata , Viet Dinh , Xiaodong Wu , Walter Heinrich Demmer
CPC分类号： H04H40/45
摘要： System and method for an all-digital audio receiver for a BTSC MTS audio signal or other composite signal that is FM modulated. A preferred embodiment comprises a digital FM demodulator for receiving an analog to digital quantized SIF signal and performing demodulation and outputting a composite audio signal, and a digital audio processor for decomposing the composite audio signal into at least the SAP, stereo and monaural signals for audio reproduction. In a preferred embodiment, the digital audio processor is a programmable digital signal processor. In a preferred embodiment, the digital FM demodulator and the digital audio processor are implemented as an integrated circuit. Methods for processing the audio signal using the digital processors of the invention are provided.
摘要翻译： 用于BTSC MTS音频信号或FM调制的其他复合信号的全数字音频接收机的系统和方法。 优选实施例包括用于接收模数数字量化SIF信号并执行解调和输出复合音频信号的数字FM解调器，以及用于将复合音频信号分解为至少SAP，用于音频的立体声和单声道信号的数字音频处理器 再生产。 在优选实施例中，数字音频处理器是可编程数字信号处理器。 在优选实施例中，数字FM解调器和数字音频处理器被实现为集成电路。 提供了使用本发明的数字处理器来处理音频信号的方法。
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公开(公告)号：US07173668B2
公开(公告)日：2007-02-06
申请号：US10623232
申请日：2003-07-18
申请人： Karl Renner , Walter Heinrich Demmer , Jason M. Meiners , Weider Peter Chang , Airong Amy Zhang
发明人： Karl Renner , Walter Heinrich Demmer , Jason M. Meiners , Weider Peter Chang , Airong Amy Zhang
CPC分类号： H04N5/10
摘要： The present invention discloses a horizontal sync detector circuit (10) comprising a filter portion (12), an equilibrium accumulator portion (14) coupled to the filter portion (12), a horizontal sync detector portion (16) coupled to the filter portion (12) and to the equilibrium accumulator portion (14), and an output logic portion (18) coupled to the horizontal sync detector portion (16), the output logic portion (18) adapted to produce a phase error (116) based on a combination of a coarse phase error (108) and a fine phase error (112).
摘要翻译： 本发明公开了一种包括滤波器部分（12），耦合到滤波器部分（12）的平衡累加器部分（14）的水平同步检测器电路（10），耦合到滤波器部分的水平同步检测器部分 12）和平衡累加器部分（14）以及耦合到水平同步检测器部分（16）的输出逻辑部分（18），输出逻辑部分（18）适于产生基于 粗相位误差（108）和精细相位误差（112）的组合。
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3.发明申请公开(公告)号：US20110131439A1
公开(公告)日：2011-06-02
申请号：US12628339
申请日：2009-12-01
申请人： Karl Renner , Walter Heinrich Demmer , Liming Xiu
发明人： Karl Renner , Walter Heinrich Demmer , Liming Xiu
摘要： Synchronous circuitry for processing digital data in which the data are filtered to compensate for expected jitter in time-average frequency clock signals. Time-average frequency synthesis circuitry generates internal clock signals of a desired frequency, for example as based on a recovered clock signal from an input data stream, in a manner in which not all periods of the clock signal are of uniform duration. A jitter precorrection filter is inserted into the data path to apply a variable delay to pre-correct for distortion caused by jitter in the clock cycle. In embodiments of the invention using a flying-adder architecture to generate the clock signal, coefficients of the digital filer realizing the jitter precorrection filter are calculated according to the currently-selected oscillator phase and according to a fractional portion of a digital frequency control word.
摘要翻译： 用于处理数字数据的同步电路，其中数据被滤波以补偿时间平均频率时钟信号中的预期抖动。 时间平均频率合成电路以不是所有的时钟信号周期具有均匀持续时间的方式，例如基于来自输入数据流的恢复的时钟信号来产生期望频率的内部时钟信号。 抖动预校正滤波器被插入到数据路径中以应用可变延迟来预校正由时钟周期中的抖动引起的失真。 在使用飞加法器架构来生成时钟信号的本发明的实施例中，根据当前选择的振荡器相位并根据数字频率控制字的小数部分来计算实现抖动预校正滤波器的数字滤波器的系数。
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公开(公告)号：US07274406B2
公开(公告)日：2007-09-25
申请号：US10713714
申请日：2003-11-14
CPC分类号： H03L7/0991 , H04N5/126
摘要： The present invention discloses a PLL (90), which may be implemented in software, hardware, or a combination of software and hardware, which comprises a sync detector (92) adapted to output a phase error (152), a vertical sync discrete time oscillator (DTO) block (98) adapted to output a vertical sync DTO (130) based on the phase error (152), and an output logic (100) adapted to detect a vertical sync based on the vertical sync DTO (130).
摘要翻译： 本发明公开了一种PLL（90），其可以以软件，硬件或软件和硬件的组合来实现，其包括适于输出相位误差（152）的同步检测器（92），垂直同步离散时间 适于基于相位误差（152）输出垂直同步DTO（130）的振荡器（DTO）块（98），以及适于基于垂直同步DTO检测垂直同步的输出逻辑（130）（130）。
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公开(公告)号：US08195972B2
公开(公告)日：2012-06-05
申请号：US12628339
申请日：2009-12-01
申请人： Karl Renner , Walter Heinrich Demmer , Liming Xiu
发明人： Karl Renner , Walter Heinrich Demmer , Liming Xiu
摘要： Synchronous circuitry for processing digital data in which the data are filtered to compensate for expected jitter in time-average frequency clock signals. Time-average frequency synthesis circuitry generates internal clock signals of a desired frequency, for example as based on a recovered clock signal from an input data stream, in a manner in which not all periods of the clock signal are of uniform duration. A jitter precorrection filter is inserted into the data path to apply a variable delay to pre-correct for distortion caused by jitter in the clock cycle. In embodiments of the invention using a flying-adder architecture to generate the clock signal, coefficients of the digital filer realizing the jitter precorrection filter are calculated according to the currently-selected oscillator phase and according to a fractional portion of a digital frequency control word.
摘要翻译： 用于处理数字数据的同步电路，其中数据被滤波以补偿时间平均频率时钟信号中的预期抖动。 时间平均频率合成电路以不是所有的时钟信号周期具有均匀持续时间的方式，例如基于来自输入数据流的恢复的时钟信号来产生期望频率的内部时钟信号。 抖动预校正滤波器被插入到数据路径中以应用可变延迟来预校正由时钟周期中的抖动引起的失真。 在使用飞加法器架构来生成时钟信号的本发明的实施例中，根据当前选择的振荡器相位并根据数字频率控制字的小数部分来计算实现抖动预校正滤波器的数字滤波器的系数。
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公开(公告)号：US07362380B2
公开(公告)日：2008-04-22
申请号：US10616754
申请日：2003-07-10
IPC分类号： H03L7/00
CPC分类号： H04N5/126 , H03L7/0991
摘要： The present invention discloses a PLL (90), which may be implemented in software, hardware, or a combination of software and hardware, which comprises a sync detector (92), a loop filter (94), a vertical sync discrete time oscillator (DTO) (98), and an output logic (100) adapted to detect a vertical sync (222), wherein the loop filter (94), the vertical sync DTO (98), and the output logic (100) are coupled to the sync detector (92).
摘要翻译： 本发明公开了一种PLL（90），其可以以软件，硬件或软件和硬件的组合来实现，其包括同步检测器（92），环路滤波器（94），垂直同步离散时间振荡器 DTO）（98）和适于检测垂直同步（222）的输出逻辑（100），其中环路滤波器（94），垂直同步DTO（98）和输出逻辑（100）耦合到 同步检测器（92）。
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7.发明授权Image scaling and sample rate conversion by interpolation with non-linear positioning vector 有权使用非线性定位向量插值的图像缩放和采样率转换公开(公告)号：US06956617B2
公开(公告)日：2005-10-18
申请号：US10004699
申请日：2001-12-04
CPC分类号： G06T3/4007 , H04N7/0135
摘要： A low-order polyphase interpolation filter, such as for decoding video and image signals, employs interpolation to facilitate sample rate conversion from a first rate to a second rate, which can be greater or less than the sample rate of the input signal. The interpolation applies interpolation coefficients, which are non-linear with respect to an associated positioning vector, to a set of input samples to provide desired scaling and/or conversion of the input sample into the desired output sample.
摘要翻译： 诸如用于解码视频和图像信号的低阶多相插值滤波器使用插值来促进从第一速率到第二速率的采样率转换，其可以大于或小于输入信号的采样率。 内插将相对于相关联的定位向量非线性的内插系数应用于一组输入样本，以将输入样本提供期望的缩放和/或转换成期望的输出样本。
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