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124 条记录 (耗时 0.028 秒)

    Method of fabricating interconnect structure
    2.
    发明授权
    Method of fabricating interconnect structure 有权
    制造互连结构的方法

    公开(公告)号：US07439154B2

    公开(公告)日：2008-10-21

    申请号：US11565632

    申请日：2006-12-01

    申请人： Feng-Yu Hsu ,  Chih-Chien Liu ,  Jim-Jey Huang ,  Jei-Ming Chen

    发明人： Feng-Yu Hsu ,  Chih-Chien Liu ,  Jim-Jey Huang ,  Jei-Ming Chen

    IPC分类号： H01L21/00 ,  H01L21/44

    CPC分类号： H01L23/53295 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for fabricating an interconnect structure is described. A substrate with a conductive part thereon is provided, a first porous low-k layer is formed on the substrate, and then a first UV-curing step is conducted. A damascene structure is formed in the first porous low-k layer to electrically connect with the conductive part, and then a first UV-absorption layer is formed on the first porous low-k layer and the damascene structure. A second porous low-k layer is formed on the first UV-absorption layer, and a second UV-curing step is conducted.

    摘要翻译： 描述了制造互连结构的方法。 提供其上具有导电部分的基板，在基板上形成第一多孔低k层，然后进行第一UV固化步骤。 在第一多孔低k层中形成镶嵌结构以与导电部分电连接，然后在第一多孔低k层和镶嵌结构上形成第一紫外线吸收层。 在第一UV吸收层上形成第二多孔低k层，进行第二UV固化步骤。

    SEMICONDUCTOR DEVICE WITH LOW-RESISTANCE INLAID COPPER/BARRIER INTERCONNECTS AND METHOD FOR MANUFACTURING THE SAME
    5.
    发明申请
    SEMICONDUCTOR DEVICE WITH LOW-RESISTANCE INLAID COPPER/BARRIER INTERCONNECTS AND METHOD FOR MANUFACTURING THE SAME 审中-公开
    具有低电阻铜/栅栏互连的半导体器件及其制造方法

    公开(公告)号：US20060199386A1

    公开(公告)日：2006-09-07

    申请号：US11164847

    申请日：2005-12-07

    申请人： Jim-Jey Huang ,  Chih-Chien Liu ,  Feng-Yu Hsu

    发明人： Jim-Jey Huang ,  Chih-Chien Liu ,  Feng-Yu Hsu

    IPC分类号： H01L21/44

    CPC分类号： H01L21/3105 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76843 ,  H01L21/76846

    摘要： An inlaid copper/barrier interconnect includes a semiconductor substrate; a carbon-doped oxide (CDO) dielectric layer disposed over the semiconductor substrate; a damascene recess etched into the CDO dielectric layer; an alpha-phase tantalum (α-Ta) single-layer barrier sputter deposited on sidewall and bottom of the damascene recess; and a conductive layer deposited directly on the alpha-phase tantalum single-layer barrier, wherein the conductive layer fills the damascene recess. According to one preferred embodiment, the alpha-phase tantalum single-layer barrier has a resistivity of about 25 μΩ-cm.

    摘要翻译： 镶嵌铜/阻挡互连件包括半导体衬底; 设置在所述半导体衬底上的碳掺杂氧化物（CDO）电介质层; 蚀刻到CDO介电层中的镶嵌凹槽; 沉积在镶嵌凹槽的侧壁和底部上的α相钽（α-Ta）单层势垒溅射; 以及直接沉积在α相钽单层屏障上的导电层，其中导电层填充镶嵌凹槽。 根据一个优选实施方案，α相钽单层势垒的电阻率为约25μΩ·cm。

    MOS TRANSISTOR AND PROCESS THEREOF
    9.
    发明申请
    MOS TRANSISTOR AND PROCESS THEREOF 审中-公开
    MOS晶体管及其工艺

    公开(公告)号：US20140042501A1

    公开(公告)日：2014-02-13

    申请号：US13571369

    申请日：2012-08-10

    申请人： Jei-Ming Chen ,  Chih-Chien Liu ,  Yu-Shu Lin ,  Tzu-Chin Wu

    发明人： Jei-Ming Chen ,  Chih-Chien Liu ,  Yu-Shu Lin ,  Tzu-Chin Wu

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/6656 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

    摘要： A MOS transistor includes a gate structure and a spacer. The gate structure is located on a substrate. The spacer is located on the substrate beside the gate structure, and the spacer includes an L-shaped inner spacer and an outer spacer, wherein the outer spacer is located on the L-shaped inner spacer, and the two ends of the L-shaped inner spacer protrude from the outer spacer. Moreover, the present invention also provides a MOS transistor process for forming the MOS transistor.

    摘要翻译： MOS晶体管包括栅极结构和间隔物。 栅极结构位于衬底上。 间隔件位于栅极结构旁边的基板上，并且间隔件包括L形内部间隔件和外部间隔件，其中外部间隔件位于L形内部间隔件上，并且L形的两个端部 内间隔件从外间隔件突出。 此外，本发明还提供一种用于形成MOS晶体管的MOS晶体管工艺。

    SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF
    10.
    发明申请
    SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF 有权
    半导体结构及其工艺

    公开(公告)号：US20130334650A1

    公开(公告)日：2013-12-19

    申请号：US13517573

    申请日：2012-06-13

    申请人： Chih-Chien Liu ,  Chia-Lung Chang ,  Jei-Ming Chen ,  Jui-Min Lee ,  Yuh-Min Lin

    发明人： Chih-Chien Liu ,  Chia-Lung Chang ,  Jei-Ming Chen ,  Jui-Min Lee ,  Yuh-Min Lin

    IPC分类号： H01L29/06 ,  H01L21/302

    CPC分类号： H01L21/76224 ,  H01L29/0649

    摘要： A semiconductor structure is located in a recess of a substrate. The semiconductor structure includes a liner, a silicon rich layer and a filling material. The liner is located on the surface of the recess. The silicon rich layer is located on the liner. The filling material is located on the silicon rich layer and fills the recess. Furthermore, a semiconductor process forming said semiconductor structure is also provided.

    摘要翻译： 半导体结构位于衬底的凹部中。 半导体结构包括衬垫，富硅层和填充材料。 衬垫位于凹槽的表面上。 富硅层位于衬套上。 填充材料位于富硅层上并填充凹槽。 此外，还提供了形成所述半导体结构的半导体工艺。