公开(公告)号：US4635261A

公开(公告)日：1987-01-06

申请号：US748885

申请日：1985-06-26

申请人： Floyd E. Anderson ,  Liang-Tsai Lin

发明人： Floyd E. Anderson ,  Liang-Tsai Lin

IPC分类号： G01R31/28 ,  G01R31/3185 ,  H01L21/66 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/118 ,  H03K19/00

CPC分类号： G01R31/318536 ,  G01R31/2884 ,  G01R31/318516

摘要： An on chip test system for arrays is provided that includes self test and maintenance operation while allowing for both synchronous and pipeline modes of normal operation. The system is integrated on a chip that includes a plurality of inputs and a plurality of outputs. A plurality of gates are coupled between the plurality of inputs and outputs wherein input signals may be transmitted asynchronously to the gates and output signals may be transmitted asynchronously to the outputs. An input shift register is coupled between each of the inputs and the gates for synchronously transmitting input signals, and an output shift register is coupled between the gates and each of the outputs for synchronously transmitting output signals. A control logic circuit is coupled to the plurality of gates, the input shift registers, and the output shift registers for selecting the systems mode of operation. A comparator circuit is coupled to the output shift registers for comparing said output signals with expected signals.

摘要翻译： 提供了阵列的片上测试系统，包括自检和维护操作，同时允许正常操作的同步和流水线模式。 该系统集成在包括多个输入和多个输出的芯片上。 多个门耦合在多个输入和输出之间，其中输入信号可以异步地发送到门，并且输出信号可以异步发送到输出。 输入移位寄存器耦合在每个输入端和栅极之间，用于同步传输输入信号，输出移位寄存器耦合在栅极和每个输出端之间，用于同步传输输出信号。 控制逻辑电路耦合到多个门，输入移位寄存器和用于选择系统操作模式的输出移位寄存器。 比较器电路耦合到输出移位寄存器，用于将所述输出信号与预期信号进行比较。

公开(公告)号：US4476401A

公开(公告)日：1984-10-09

申请号：US462574

申请日：1983-01-31

申请人： Liang-Tsai Lin

发明人： Liang-Tsai Lin

IPC分类号： G11C7/22 ,  H03K5/156 ,  H03K3/86 ,  H03K5/06

CPC分类号： G11C7/22 ,  H03K5/1565

摘要： An on-chip memory control circuit generates a proper WRITE STROBE signal for a clock synchronized pipe-line operated integrated circuit memory. A symmetrical clock signal having half the frequency of the system clock is produced by applying the system clock to the C input of a standard master slave delay type flip-flop having its Q output fed back to its D input. A negative going pulse train .phi..sub.P comprising a pulse at every transition of the symmetrical clock is generated by a level change detector which issues a pulse of a desired width whenever a level change at its input is detected. A delayed pulse train .phi..sub.PD is produced by delaying .phi..sub.P an amount which depends on the speed of the memory and other design criteria. The pulse drains .phi..sub.P and .phi..sub.PD are applied to an asynchronous flip-flop, the output of which corresponds to the desired WRITE STROBE signal.

摘要翻译： 片上存储器控制电路为时钟同步管线操作的集成电路存储器生成适当的WRITE STROBE信号。 将系统时钟的一半频率的对称时钟信号通过将系统时钟应用到具有反馈到其D输入的＆upbar＆Q输出的标准主从延迟型触发器的C输入端来产生。 在对称时钟的每个转变处包括脉冲的负向脉冲串phi P由电平变化检测器产生，电平变化检测器每当检测到其输入端的电平变化时发出期望宽度的脉冲。 延迟脉冲串phi PD是通过延迟phi P一个取决于存储器的速度和其他设计标准的量来产生的。 脉冲排出phi P和phi PD被施加到异步触发器，其输出对应于期望的WRITE STROBE信号。